Parallel processing computer systems with reduced power consumption and methods for providing the same

A parallel processing computing system comprising:

• (a) an ordered set of m memory banks including a first and last memory bank, wherein m is an integer greater than 1;
• (b) a processor core that implements (i) n ordered virtual processors, and (ii) a pipeline having p ordered stages, including a memory command stage;
• and
• (c) a network-on-chip connected to the processor core and the memory banks through an JO processor,
• wherein n is an integer greater than 1, and p is an integer less than or equal to n,
• wherein the memory banks are the most local data memory to the processor core, and are connected to the processor core through the IO processor,
• wherein each of the memory banks operates in a pipelined fashion comprising b stages to achieve a memory access rate providing a number of memory accesses per second,
• wherein the processor core clock speed is faster than the memory access rate of the memory banks by an integer multiple k, and a memory bank access causes the bank to be unavailable for k cycles and the result of the memory bank access to be available in k*b cycles,
• wherein each virtual processor is assigned in order to one of the memory banks in order,
• wherein after the last memory bank is assigned, the next virtual processor is assigned to the first memory bank, and
• wherein the multiple virtual processors and their respective memory banks are adapted to simultaneously execute independent threads, and each virtual processor is adapted to execute pipeline stages in order and no virtual processor executes the same pipeline stage as any other virtual processor at the same time.