Higher-level redundancy information computation
AssigneeLSI Corporation
InventorsJeremy Isaac Nathaniel WERNER, Leonid BARYUDIN, Timothy Lawrence CANEPA, Earl T. COHEN
Life of this patent
Estimating the term…
Loading patent…
AssigneeLSI Corporation
InventorsJeremy Isaac Nathaniel WERNER, Leonid BARYUDIN, Timothy Lawrence CANEPA, Earl T. COHEN
Estimating the term…
Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD. A first portion of higher-level redundancy information is computed using parity coding via an XOR of all pages in a portion of data to be protected by the higher-level redundancy information. A second portion of the higher-level redundancy information is computed using a weighted-sum technique, each page in the portion being assigned a unique non-zero “index” as a weight when computing the weighted-sum. Arithmetic is performed over a finite field (such as a Galois Field). The portions of the higher-level redundancy information are computable in any order, such as an order based on order of read operation completion of non-volatile memory elements.
(canceled)
A method comprising:
A non-transitory computer readable medium having a set of instructions stored therein that when executed by a processing element cause the processing element to perform operations comprising:
A device for use coupled to one or more flash memories external to the device, the device comprising:
Dependencies are inferred from the claim text.