US 2014/0237163 A1 · REDUCING WRITES TO SOLID STATE DRIVE CACHE MEMORIES OF STORAGE CONTROLLERS

Abstract

Methods and structure are provided for reducing the number of writes to a cache of a storage controller. One exemplary embodiment includes a storage controller that has a non-volatile flash cache memory, a primary memory that is distinct from the cache memory, and a memory manager. The memory manager is able to receive data for storage in the cache memory, to generate a hash key from the received data, and to compare the hash key to hash values for entries in the cache memory. The memory manager can write the received data to the cache memory if the hash key does not match one of the hash values. Also, the memory manager can modify the primary memory instead of writing to the cache if the hash key matches a hash value, in order to reduce the amount of data written to the cache memory.

Claims20

Dependent claims

A storage controller comprising:

a non-volatile flash cache memory;
a primary memory that is distinct from the cache memory;
and
a memory manager operable to receive data for storage in the cache memory, to generate a hash key from the received data, to compare the hash key to hash values for entries in the cache memory, to write the received data to the cache memory if the hash key does not match one of the hash values, and to modify the primary memory instead of writing to the cache if the hash key matches a hash value in order to reduce the amount of data written to the cache memory.

1 more element

Dependencies are inferred from the claim text.

Reducing writes to solid state drive cache memories of storage controllers

Life of this patent

Reducing writes to solid state drive cache memories of storage controllers

Life of this patent

Abstract

Claims20