Providing A Peripheral Component Interconnect (PCI)-Compatible Transaction Level Protocol For A System On A Chip (SoC)

A system comprising:

• a processor;
• a host interface coupled to the processor, the host interface to couple the processor to a memory;
• an adapter coupled to the host interface to communicate with the host interface according to a peripheral component interconnect (PCI)-compliant protocol and to communicate with a second interface according to a non-PCI-compliant protocol;
• the second interface coupled to the adapter and to perform a conversion of a transaction from the adapter to a second transaction and to perform address translation between a re-locatable address and a fixed address;
• and
• a first physical unit coupled between the second interface and an interconnect to communicate transactions between the second interface and the interconnect, wherein the interconnect is to couple the second interface to a plurality of second physical units each to couple to one of a plurality of heterogeneous resources, each of the plurality of heterogeneous resources including an intellectual property (IP) core and an interface logic, wherein the system is to operate in accordance with the PCI-compliant protocol and the IP core is to operate in accordance with the non-PCI-compliant protocol.

A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

• converting a peripheral component interconnect (PCI) transaction to a transaction having a format for a non-PCI protocol and performing an address translation between a re-locatable address and a fixed address for an intellectual property (IP) core that operates according to the second protocol, via a first interface;
• communicating the transaction between the first interface and an interconnect via a first physical unit coupled between the first interface and the interconnect;
• and
• implementing a PCI header of the PCI protocol for the IP core via an interface logic coupled to the interconnect.