Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Computer System

A system-on-chip (SoC) comprising:

• a processor adapted on a semiconductor die;
• a host interface adapted on the semiconductor die to couple to the processor, the host interface to couple the processor to a memory and an adapter;
• the adapter to couple to the host interface to communicate with the host interface via a first interconnect to operate according to a peripheral component interconnect express (PCIe)-compatible protocol and to communicate with a second interface via a second interconnect to operate according to an advanced extensible interface (AXI)/open core protocol (OCP)-compatible protocol;
• the second interface adapted on the semiconductor die to couple to the adapter, the second interface to perform common functionality for a plurality of heterogeneous resources to couple to a third interconnect;
• and
• the third interconnect adapted on the semiconductor die to couple the second interface to the plurality of heterogeneous resources, each of the plurality of heterogeneous resources including a core and an interface logic, wherein the SoC is to operate according to the PCIe-compatible protocol and at least one of the cores is to operate according to the AXI/OCP protocol.

A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

• communicating, via an adapter of a system on a chip (SoC), with a first component according to a peripheral component interconnect (PCI)-compatible protocol and communicating with a first interface according to a second protocol;
• performing address translation and ordering of transactions received from the first component in the first interface;
• translating configuration cycles of the PCI-compatible protocol into a format for the second protocol;
• and
• communicating between the first interface and a plurality of heterogeneous resources, via an interconnect, each of the plurality of heterogeneous resources including a core and an interface logic, wherein the SoC is to operate according to the PCI-compatible protocol and at least some of the cores to operate according to the second protocol.