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US 2014/0237152 A1Published application
Folded Memory Modules
AssigneeRambus Inc.
InventorsAMIR AMIRKHANY, SURESH RAJAN, RAVINDRANATH KOLLIPARA, IAN SHAEFFER, DAVID A. SECKER
Life of this patent
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Abstract
A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.
Claims16
A memory module comprising:
- a data interface including a plurality of data pins;
- a data path including a plurality of data lines, each of the plurality of data lines corresponding to one of the plurality of data pins;
- a plurality of configurable switches coupled between the data interface and the data path, each of the configurable switches coupled between one of the plurality of data pins and a corresponding one of the plurality of data lines and when enabled coupling said one of the plurality of data pins to said corresponding one of the plurality of data lines, and when disabled decoupling said one of the plurality of data pins from said corresponding one of the plurality of data lines;
- and
- a plurality of memories to store data received from the data path in response to a write command and to output the data to the data path in response to a read command.
2 more elements
A memory system, comprising:
- a motherboard comprising a plurality of data lines each coupled to a first memory module slot and to a second memory module slot;
- a first memory module coupled to the plurality of data lines via the first memory module slot, the first memory module comprising a first memory core associated with a first rank and a second memory core associated with a second rank, the first memory module including a first data path to couple a first subset of the plurality of data lines to the first memory core and to the second memory core;
- a second memory module coupled to the plurality of data lines via the second memory module slot, the second memory module comprising a third memory core associated with the first rank and a fourth memory core associated with the second rank, the second memory module including a second data path to couple a second subset of the plurality of data lines to the third memory core and to the fourth memory core.
A buffer, comprising:
- a mode register to enable or disable one or more of a plurality of configurable switches;
- memory controller side data lines coupled to the plurality of configurable switches, the memory controller side data lines including a first subset of the memory controller side data lines coupled to enabled switches of the plurality of configurable switches, and the memory controller side data lines including a second subset of the memory controller side data lines coupled to disabled switches of the plurality of configurable switches, the first subset of the memory controller side data lines configured to communicate data to and from a memory controller;
- memory core side data lines to communicate the data to and from one or more memory cores;
- a data router coupled between the memory controller side data lines and the memory core side data lines, the data router to route the data between the first subset of the memory controller side data lines and a first subset of the memory core side data lines during a first time, and to route the data between the first subset of the memory controller side data lines and a second subset of the memory core side data lines during a second time.
1 more element
Dependencies are inferred from the claim text.