Pseudo-random bit sequence generator
AssigneeAltera Canada Co.
InventorJunjie Yan
Life of this patent
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Abstract
The present invention discloses a pseudo-random bit sequence (PRBS) generator which outputs the entire datapath, or entire pseudo-random bit sequence, over one single clock cycle. This is accomplished by removing redundancy, or any redundant exclusive-or gates from linear feedback shift registers; using logic to identify the critical path and optimal shift for the critical path; and dividing the datapath into several pipeline stages to increase the clock rate (i.e., transmission speed).
Claims21
1-5. (canceled)
Bit sequence generation circuitry comprising:
- linear feedback shift register circuitry configured to store a current state data;
- and
- combinational logic circuitry configured to:
- receive the current state data from the linear feedback shift register circuitry;
- determine a next state data by processing the current state data;
- and
- provide the next state data to the linear feedback shift register circuitry, wherein said providing the next state data comprises shifting elements in registers of the linear feedback shift register circuitry by an optimal bit-shift, wherein said optimal bit-shift is equivalent to a maximum number of logic gates between said registers in the linear feedback shift register circuitry after removing redundant logic gates in the linear feedback shift register circuitry.
Bit sequence generation circuitry comprising:
- combinational logic circuitry configured to:
- receive a current state data stored in linear feedback shift register circuitry;
- determine a next state data by processing the current state data;
- and
- provide the next state data to the linear feedback shift register circuitry;
- and
- the linear feedback shift register circuitry configured to:
- receive the next state data from the combinational logic circuitry;
- and
- replace the stored current state data with the received next state data, wherein said replacing comprises shifting elements in registers of the linear feedback shift register circuitry by an optimal bit-shift, wherein said optimal bit-shift is equivalent to a maximum number of logic gates between said registers in the linear feedback shift register circuitry after removing redundant logic gates.
A method for generating a bit sequence comprising:
- transmitting current state data to combinational logic circuitry;
- receiving next state data from the combinational logic circuitry, wherein the next state data is determined by processing the current state data;
- and
- replacing the current state data stored in linear feedback shift register circuitry with the received next state data, wherein said replacing comprises shifting elements in registers of the linear feedback shift register circuitry by an optimal bit-shift, wherein said optimal bit-shift is equivalent to a maximum number of logic gates between said registers in the linear feedback shift register circuitry after removing redundant logic gates.
Dependencies are inferred from the claim text.