Test architecture having multiple fpga based hardware accelerator blocks for testing multiple duts independently

A method for testing using an automated test equipment (ATE) comprising:

• transmitting instructions from a system controller of a computer system to a tester processor, wherein said tester processor is operable to generate commands and data from said instructions for coordinating testing of a plurality of devices under test (DUTs);
• generating commands and data transparently from said tester processor for testing of a plurality of DUTs using hardware accelerator circuits programmed within a plurality of FPGA components, wherein said plurality of FPGA components is communicatively coupled to said tester processor via a bus and wherein each hardware accelerator circuit is operable to test a DUT of said plurality of DUTs;
• communicating with a respective DUT through an I/O port, wherein said I/O port is communicatively coupled to a respective FPGA of said plurality of FPGAs;
• and
• operating the tester processor in one of a plurality of functional modes, said plurality of functional modes configured to allocate functionality for generating commands and data between said tester processor and said plurality of FPGA components.

A tester comprising:

• a system controller for controlling a test program for testing a plurality of DUTs;
• a plurality of modules operable to interface with and test said plurality of DUTs, said plurality of modules coupled to said system controller via a first communication bus and wherein each module comprises:
• a tester processor coupled to communicate with said system controller to receive instructions and data therefrom in accordance with said test program;
• a plurality of programmable instantiated tester blocks coupled to said tester processor via a second bus, each programmable instantiated tester block operable to generate test data for application to a respective DUT in a way transparent to said test processor, further operable to receive and compare test data generated by said respective DUT in a way transparent to said tester processor, and further yet operable to be programmed to communicate with said respective DUT in a communication protocol compatible with said respective DUT;
• a local memory coupled to said plurality of programmable instantiated tester blocks for storing test data therein;
• and
• a plurality of IO ports for coupling said plurality of DUTs to said plurality of modules wherein each respective programmable instantiated tester block is operable to control at least one respective DUT of said plurality of DUTs.