Tester with acceleration on memory and acceleration for automatic pattern generation within a fpga block

A testing method using an automated test equipment (ATE), said method comprising:

• generating commands for routing data to a plurality of DUTs using a tester processor coupled to a plurality of instantiated FPGA blocks of a module;
• automatically generating test pattern data using a pattern generator circuit programmed onto a first instantiated FPGA block of said plurality of instantiated FPGA blocks;
• routing said test pattern data to a first DUT from said plurality of DUTs in accordance with said commands generated by said tester processor;
• reading data from said first DUT in accordance with said commands generated by said tester processor;
• and
• comparing said test pattern data written to said first DUT with said data read from said first DUT using a comparator circuit programmed onto said first instantiated FPGA block.

An automated test equipment (ATE) apparatus comprising:

• a computer system comprising a tester processor, wherein said tester processor is communicatively coupled to a plurality of FPGA components, wherein each of said plurality of FPGA components is coupled to a memory module and comprises:
• an upstream port operable to receive commands and data from said tester processor;
• a downstream port operable to communicate with a respective DUT from a plurality of DUTs;
• a plurality of hardware accelerator circuits, wherein each of said plurality of hardware accelerator circuits is configured to communicate with one of said plurality of DUTs, and further wherein each of said plurality of hardware accelerator circuits comprises:
• a memory control circuit configured to read test pattern data to be written to said one of the plurality of DUTs from said memory module;
• and
• a comparator circuit configured to compare said test pattern data written to said one of the plurality of DUTs with test pattern data read from said one of the plurality of DUTs.

A testing method using an automated test equipment (ATE), said method comprising:

• generating commands for routing data to a plurality of DUTs using a tester processor coupled to a plurality of instantiated FPGA blocks of a module;
• automatically reading test pattern data from a memory module coupled to a first instantiated FPGA block of said plurality of instantiated FPGA blocks using a memory control circuit programmed onto said first instantiated FPGA block;
• routing said test pattern data to a first DUT from said plurality of DUTs in accordance with said commands generated by said tester processor;
• reading data from said first DUT in accordance with said commands generated by said tester processor;
• and
• comparing said test pattern data written to said first DUT with said data read from said first DUT using a comparator circuit programmed onto said first instantiated FPGA block.