Method of Semiconductor Integrated Circuit Fabrication
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChing-Fu Yeh, Hsiang-Huan Lee, Chao-Hsian Peng, Hsien-Chang Wu
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Abstract
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.
Claims20
A method for fabricating a semiconductor integrated circuit (IC), the method comprising:
- providing a substrate;
- depositing a conductive layer on the substrate;
- forming a patterned hard mask on the conductive layer;
- forming a catalyst layer on the conductive layer in a vertical interconnection region;
- growing a plurality of carbon nanotubes (CNTs) from the catalyst layer;
- and p1 etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.
A method for fabricating a semiconductor integrated circuit (IC), the method comprising:
- providing a substrate having a conductive feature;
- depositing a conductive layer on the substrate;
- depositing a carbon-containing hard mask on the conductive layer;
- patterning the carbon-containing hard mask;
- coating a photoresist on the patterned carbon-containing hard mask and the conductive layer;
- patterning the photoresist to have an opening to expose at least a portion of the conductive layer such that the portion aligns to the conductive feature on the substrate;
- depositing a catalyst layer on the conductive layer in the photoresist opening;
- removing the patterned photoresist;
- after removing the patterned photoresist, growing a plurality of carbon nanotubes (CNTs) from the catalyst layer;
- etching the conductive layer by using the CNTs and the patterned hard mask as etching mask to form metal features;
- and
- depositing an inter-level dielectric (ILD) layer between metal features on the substrate.
A method for fabricating a semiconductor integrated circuit (IC), the method comprising:
- providing a substrate;
- depositing a conductive layer on the substrate;
- forming a patterned hard mask on the conductive layer to define a first region;
- forming a patterned photoresist layer on the conductive layer to define a second region;
- forming a catalyst layer on the conductive layer in the first and second regions;
- growing a plurality of carbon nanotubes (CNTs) from the catalyst layer;
- and
- etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.
Dependencies are inferred from the claim text.