Method of integrating a charge-trapping gate stack into a cmos flow

A method comprising:

• forming a dielectric stack on a surface of a substrate, the dielectric stack including a tunneling dielectric overlying the surface of the substrate and a charge-trapping layer overlying the tunneling dielectric;
• forming a cap layer overlying the dielectric stack, wherein the cap layer comprises a multi-layer cap layer including at least a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer;
• patterning the cap layer and the dielectric stack to form a gate stack of a memory device;
• removing the second cap layer;
• and
• performing an oxidation process to oxidize the first cap layer to form a blocking oxide overlying the charge-trapping layer, wherein the oxidation process consumes the first cap layer.

A method comprising:

• forming a dielectric stack on a surface of a substrate, the dielectric stack including a tunneling dielectric overlying the surface of the substrate and a charge-trapping layer on the tunneling dielectric;
• forming a cap layer on the charge-trapping layer;
• patterning the cap layer and the dielectric stack to form a gate stack of a memory device in a first region of the substrate and to remove the cap layer and the charge-trapping layer from a second region of the substrate;
• and
• removing at least a portion of the cap layer;
• performing an oxidation process to form a gate oxide overlying the surface of the substrate in the second region while concurrently oxidizing a remaining portion of the cap layer to form a blocking oxide on the charge-trapping layer.

A method comprising:

• forming a dielectric stack in at least a first region of a substrate, the dielectric stack including a tunneling dielectric overlying a surface of the substrate and a charge-trapping layer on the tunneling dielectric;
• forming a cap layer overlying the dielectric stack;
• forming a sacrificial oxide over the cap layer;
• patterning the sacrificial oxide, cap layer and dielectric stack to form a gate stack in the first region of the substrate, and to remove the sacrificial oxide, cap layer and dielectric stack from a second region of the substrate;
• removing the sacrificial oxide from the gate stack while removing an oxide from the second region;
• and
• forming a gate oxide overlying the surface of the substrate in the second region using an oxidation process while concurrently oxidizing at least a portion of the cap layer to form a blocking oxide overlying the charge-trapping layer.