Double gate ion sensitive field effect transistor
AssigneeStc.Unm
InventorsPayman Zarkesh-Ha, Steven R.J. Brueck, Jeremy Edwards
Life of this patent
Estimating the term…
Abstract
Devices that include a substrate; a source region and a drain region formed within the substrate and having a channel region provided therebetween; a first insulating layer formed over the channel region; a first floating gate formed over the first insulating layer, the first floating gate configured to respond to an analyte in a target material; and a second gate formed over the first floating gate, the second gate capacatively coupled but not electrically connected to the first floating gate.
Claims23
A device comprising:
- a substrate;
- a source region and a drain region formed within the substrate and having a channel region provided therebetween;
- a first insulating layer formed over the channel region;
- a first floating gate formed over the first insulating layer, the first floating gate configured to respond to an analyte in a target material;
- a second gate formed over the first floating gate, the second gate capacatively coupled but not electrically connected to the first floating gate.
A method of determining the concentration of an analyte in a target material, the method comprising the steps of:
- providing a device, the device comprising:
- a substrate;
- a source region and a drain region formed within the substrate and having a channel region provided therebetween;
- a first insulating layer formed over the channel region;
- a first floating gate formed over the first insulating layer, the first floating gate configured to respond to an analyte in a target material;
- a second gate formed over the first floating gate, the second gate capacatively coupled but not electrically connected to the first floating gate;
- applying a potential of about 0 V to the second gate;
- monitoring the current flowing through the channel region between the source and the drain;
- and
- determining the concentration of the analyte in the target material based on the monitored current.
An array comprising:
- a plurality of devices, each of the plurality of devices comprising:
- a substrate;
- a source region and a drain region formed within the substrate and having a channel region provided therebetween;
- a first insulating layer formed over the channel region;
- a first floating gate formed over the first insulating layer, the first floating gate configured to respond to an analyte in a target material;
- and
- a second gate formed over the first floating gate, the second gate capacatively coupled but not electrically connected to the first floating gate;
- and
- at least one readout circuit, the readout circuit configured to monitor current flowing through the channel region between the source and the drain in at least one of the plurality of devices.
Dependencies are inferred from the claim text.