Header processing engine

A header processing engine for performing header processing of a sequence of data packets each having multiple headers, the header processing engine comprising:

• a header recognizer configured to parse the headers of each data packet in a sequence of data packets and, for each data packet, form one or more messages indicating the type and position of each header in the data packet, the header recognizer being configured to parse the data packets in sequence;
• and
• a processor configured to perform header processing on each data packet of the sequence in dependence on the one or more messages formed for that data packet and provide in sequence at its output processed data packets;
• wherein the header recognizer and the processor are configured to operate in parallel so as to allow the processor to perform header processing on the data packets out of sequence.

A header processing engine for performing header processing of a sequence of data packets stored at a buffer, each of the data packets having multiple headers and the header processing engine comprising:

• a processor having an execution pipeline;
• and
• a pre-processor unit configured to parse the headers of a data packet stored at the buffer and, in dependence on the types of headers in the data packet, form a data structure identifying a set of instructions, the data structure being such as to be operable to cause the processor to effect processing of the headers of the data packet without accessing the data packet stored at the buffer;
• wherein the processor is configured to access the data structure and execute the said set of instructions so as to process the headers of the data packet.

A processor configured for processing network data packets and comprising:

• an instruction memory storing a plurality of instruction sequences;
• a processor memory for storing a plurality of instruction references and sets of state of the processor, each instruction reference identifying an instruction sequence stored at the instruction memory and each set of state corresponding to an instruction reference;
• and
• an execution pipeline operable to execute an instruction sequence identified by an instruction reference using the corresponding set of state stored at the processor memory, an instruction sequence and its corresponding state defining an execution thread for processing a particular network data packet;
• the processor being configured to be operable to, during processing of a first network data packet by executing an instruction sequence identified by a first instruction reference, switch execution threads so as to process a second network data packet by:
• writing the state of the execution pipeline to a first set of state at the processor memory;
• loading a second set of state into the execution pipeline from the processor memory;
• and
• executing a second instruction sequence identified by an instruction reference corresponding to the second set of state;
• wherein the processor is configured to switch execution threads on initiating execution of one or more predetermined instructions in an instruction sequence.

A method for switching between execution threads at a processor configured for processing network data packets and having an execution pipeline, an instruction memory storing a plurality of instruction sequences, and a processor memory storing first and second instruction references and corresponding first and second sets of state of the processor, each instruction reference identifying an instruction sequence stored at the instruction memory and each instruction sequence and its corresponding state defining an execution thread for processing a particular network data packet, the method comprising:

• during processing of a first network data packet by executing at the execution pipeline the instruction sequence identified by the first instruction reference, pausing execution at the execution pipeline;
• writing the state of the execution pipeline to the first set of state at the processor memory;
• loading the second set of state into the execution pipeline from the processor memory;
• and
• executing at the execution pipeline the instruction sequence identified by the second instruction reference so as to effect processing of a second network data packet.