Management of Traffic Buffering in Internal and External Memories in a Passive Optical Network

An optical network unit (ONU), comprising:

• a chip comprising a first memory, wherein the chip further comprises a receiver configured to receive a plurality of data packets from a stream of packets;
• a second memory external to the chip;
• and
• a packet microprocessor configured to:
• store a plurality of packet descriptors associated with each data packet in a configurable first queue in the first memory, wherein the first queue includes a plurality of cache slots,
• identify a state of the first queue;
• and
• in response to the state of the first queue meeting a predetermined threshold, transfer packet descriptors from a tail cache slot of the first queue to a second queue in the second memory.

A computer program product having computer logic stored therein, said control logic when executed causing a processor to perform operations for managing memory in a passive optical network (PON), the operations comprising:

• receiving a plurality of data packets;
• storing a plurality of packet descriptors associated with each data packet in a configurable first queue, wherein the first queue includes a plurality of cache slots and is managed in an internal memory;
• identifying a state of the first queue;
• and
• in response to the state of the first queue meeting a predetermined threshold, transferring packet descriptors from a tail cache slot of the first queue to a second queue, wherein the second queue is managed in an external memory.