Apparatus and method to reduce bit line disturbs
AssigneeSpansion LLC
InventorsAmichai GIVANT, Ilan BLOOM, Mark RANDOLPH, Zhizheng LIU
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Abstract
A non-volatile memory device comprising a memory cell array including a plurality of non-volatile memory cells arranged in rows and columns, wherein memory cells arranged in a same row share a word line and memory cells arranged in a same column share a bit line; and at least an address decoder to provide a negative voltage to at least one non-accessed word line in said array when a programming or erasure voltage is provided along a shared bit line.
Claims18
A non-volatile memory device comprising:
- a memory cell array including a plurality of non-volatile memory cells arranged in rows and columns, wherein memory cells arranged in a same row share a word line and memory cells arranged in a same column share a bit line;
- and
- at least an address decoder to provide a negative voltage to at least one non-accessed word line in said array when a programming or erasure voltage is provided along a shared bit line.
A non-volatile memory device comprising:
- a memory cell array comprising a plurality of sectors of non-volatile memory cells which share bit lines, of which one of said sectors is an active sector and the rest are non-active sectors;
- and
- at least an address decoder to provide a negative voltage to word lines in said non-active sectors when one of a programming voltage or an erasure voltage is provided along one of said shared bit lines.
A non-volatile memory device comprising:
- a memory cell array including a plurality of non-volatile memory cells arranged in rows and columns, wherein memory cells arranged in a same row share a word line and memory cells arranged in a same column share a bit line;
- and
- a bit-line decoder to provide a positive voltage to a source bit line while said one of a programming voltage or erasure voltage is provided to a drain bit line.
A non-volatile memory device comprising:
- a multiplicity of bit lines where source and drain bit lines alternate;
- and
- a plurality of two bit, non-volatile memory cells which share bit lines, of which one bit of each cell is a non-data bit located near a source bit line and one bit of each cell is a data bit located near a drain bit line, where said non-data bits are slightly programmed
A method of reducing bit line disturbs in non-volatile memory cell in a memory array including a plurality of non-volatile memory cells arranged in rows and columns, wherein memory cells arranged in a same row share a word line and memory cells arranged in a same column share a bit line, comprising providing a negative voltage to non-accessed word lines in said array when a programming or erasure voltage is provided along a shared bit line
A method of reducing bit line disturbs in non-volatile memory cells in a plurality of sectors of non-volatile memory cells which share bit lines, of which one of said sectors is an active sector and the rest are non-active sectors, comprising providing a negative voltage to word lines in said non-active sectors when one of a programming voltage or an erasure voltage is provided along one of said shared bit lines.
Dependencies are inferred from the claim text.