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US 2014/0233338 A1Published application
Memory apparatus and system with shared wordline decoder
AssigneeMicron Technology, Inc.
InventorsGerald Barkley, Efrem Bolandrina, Daniele Vimercati
Life of this patent
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Abstract
A memory device includes wordline decoder circuits that share components between adjacent memory blocks. The wordline decoder circuits include multiple levels, where at least one level is split, driving half of the wordlines in one adjacent memory block and driving half of the wordlines in another adjacent memory block. Memory blocks have every other wordline coupled to one adjacent decoder circuit, and the remaining wordlines coupled to another adjacent decoder circuit.
Claims20
An apparatus, comprising:
- a decoder circuit coupled to a first memory block and a second memory block, the decoder circuit configured to select wordlines of the first memory block responsive to a first section of a first level decoder being enabled, and to select wordlines of the second memory block responsive to a second section of the first level decoder being enabled.
A method, comprising:
- enabling a second level decoder;
- and
- enabling a first section of a first level decoder to select half of a plurality of wordlines of a first memory block.
An apparatus, comprising:
- a decoder circuit including a second level decoder shared between first and second sections of a first level decoder, the first section of the first level decoder coupled to half of a plurality of wordlines of a first memory block and the second section of the first level decoder coupled to half of a plurality of wordlines of a second memory block that is adjacent the first memory block.
Dependencies are inferred from the claim text.