Semiconductor device and method of controlling the same
AssigneeElpida Memory, Inc.
InventorsKinu MATSUNAGA, Hiroshi AKAMATSU
Life of this patent
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Abstract
A device includes a command decoder that is configured to output, in a normal operation mode, a precharge signal in response to a first type transition edge of a synchronous signal, and an active signal in response to a next first type transition edge that is next to the first type transition edge. The command decoder is configured to output, in a test mode, the precharge signal in response to a second type transition edge of the synchronous signal, and the active signal in response to a next first type transition edge that is next to the second type transition edge.
Claims20
A device comprising:
- a command decoder configured to output, in a first operation mode, a first signal in response to a first transition edge of a first type of transition edge of a synchronous signal, and a second signal in response to a second transition edge of the first type of transition edge of the synchronous signal, wherein the first transition edge and the second transition edge are consecutive;
- wherein the command decoder is configured to output, in a second operation mode, the first signal in response to a third transition edge of a second type of transition edge of the synchronous signal different from the first type of transition edge, and the second signal in response to a fourth transition edge of the first type of transition edge of the synchronous signal, and wherein the third transition edge and the fourth transition edge are consecutive.
A device comprising:
- a command decoder configured to output a first signal and a second signal in synchronization with a clock;
- wherein a first time period between outputting the first signal and outputting the second signal in a first operation mode is greater than a second time period between outputting the first signal and outputting the second signal in a second operation mode.
A method of controlling a device, the method comprising:
- in a first operation mode, outputting a first signal in response to a first transition edge of a first type of transition edge of a synchronous signal, and a second signal in response to a second transition edge of the first type of transition edge of the synchronous signal, wherein the first transition edge and the second transition edge are consecutive;
- in a second operation mode, outputting the first signal in response to a third transition edge of a second type of transition edge of the synchronous signal, and the second signal in response to a fourth transition edge of the first type of transition edge of the synchronous signal, wherein the third transition edge and the fourth transition edge are consecutive.
Dependencies are inferred from the claim text.