Write assist circuit, memory device and method

A memory device, comprising:

• a memory array comprising:
• a plurality of memory cells arranged in a plurality of columns, and
• a plurality of cell supply voltage rails each coupled to the memory cells in one of the columns;
• and
• a write assist circuit comprising:
• a bias voltage circuit common to the columns in the memory array and configured to generate, at an output thereof, an adjustable bias voltage, and
• a plurality of supply voltage switching circuits each corresponding to one of the columns of the memory array and configured to
• connect the cell supply voltage rail of the corresponding column to the output of the bias voltage circuit in response to the column selected for writing, and
• connect the cell supply voltage rail of the corresponding column to a power supply voltage node having a power supply voltage higher than the bias voltage in response to the column not selected for writing.

A write assist method, comprising:

• selecting one or more columns among a plurality of columns of a memory device for a write operation;
• connecting cell supply voltage nodes of memory cells of one or more unselected columns among the columns of the memory device to a power supply voltage node to apply a power supply voltage on the power supply voltage node to the cell supply voltage nodes of the memory cells of the one or more unselected columns;
• and
• connecting cell supply voltage nodes of memory cells of the one or more selected columns to an output of a bias voltage circuit shared by the columns in the memory device to apply an adjustable bias voltage at the output of the bias voltage circuit to the cell supply voltage nodes of the memory cells of the one or more selected columns, the adjustable bias voltage lower than the power supply voltage.