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US 2014/0233318 A1Published application
Dynamic data caches, decoders and decoding methods
AssigneeMicron Technology, Inc.
InventorChang Wan Ha
Life of this patent
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Abstract
Examples described include dynamic data caches (DDCs), decoders and decoding methods that may fit into a smaller width area. The DDCs, decoders and decoding method may be used in flash memory devices. A single column select line may be provided to select a plurality of cached bytes, while a second select line selects a byte of the selected plurality. The column select line may be routed parallel to bit lines carrying data, while the second select line may be routed perpendicular to the bit lines.
Claims20
A cache access circuit comprising:
- a data input/output line;
- a cache line;
- a first transistor having a source/drain terminal coupled to the data input/output line, wherein the first transistor is configured to receive a first select signal at its gate terminal;
- and
- a second transistor having a first source/drain terminal coupled to the source/drain terminal of the first transistor and a second source/drain terminal coupled to the cache line, wherein the second transistor is configured to receive a second select signal at its gate terminal;
- wherein the first select signal is configured to select a group of bytes, and the second select signal is configured to select a particular byte within the group of bytes.
3 more elements
A method for accessing a dynamic data cache, the method comprising:
- providing a first signal configured to select a plurality of bytes of the dynamic data cache to an access circuit;
- providing a second signal configured to select one of the bytes of the plurality of bytes to the access circuit;
- wherein a data input/output line is coupled to a data cache responsive to both the first and second signals.
An apparatus comprising:
- a first transistor coupled to a data line, wherein the first transistor is configured to be enabled responsive to a first signal;
- and
- a second transistor coupled between the first transistor and a cache line, wherein the second transistor is configured to be enabled responsive to a second signal;
- wherein a combination of the first signal and the second signal selects a particular byte of a group of bytes.
1 more element
Dependencies are inferred from the claim text.