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US 2014/0233309 A1Published application
Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorNoboru SHIBATA
Life of this patent
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Abstract
According to one embodiment, a semiconductor includes a memory cell, a bit line, a word line, a sense amplifier, and a control circuit. The memory cell stores n levels (where n is a natural number of two or greater). The control circuit controls potentials of the word line and the bit line. In a read of k−1 levels (k≦n) stored in the memory cell, the control circuit, upon applying a given voltage to the word line, determines read data based on first data corresponding to the voltage of the bit line read at a first timing by the sense amplifier and second data corresponding to the voltage of the bit line read, by the sense amplifier, at a second timing different from the first timing.
Claims11
A semiconductor memory device comprising:
- a memory cell configured to stores n levels (where n is a natural number of two or greater);
- a bit line connected to the memory cell;
- a word line connected to the memory cell;
- a sense amplifier connected to the bit line to detect a voltage of the bit line;
- and
- a control circuit configured to control potentials of the word line and the bit line,
- wherein, in a read of k−1 levels (k≦n) stored in the memory cell, the control circuit, upon applying a given voltage to the word line, determines read data based on first data corresponding to the voltage of the bit line read at a first timing by the sense amplifier and second data corresponding to the voltage of the bit line read, by the sense amplifier, at a second timing different from the first timing.
4 more elements
A semiconductor memory device comprising:
- a memory cell configured to stores n levels (where n is a natural number of two or greater);
- a bit line connected to the memory cell;
- a word line connected to the memory cell;
- a sense amplifier connected to the bit line to detect a voltage of the bit line;
- and
- a control circuit configured to control potentials of the word line and the bit line,
- wherein the control circuit sets an optimum read level based on first data read from the memory cell at a first timing, second data read from the memory cell at a second timing different from the first timing, and kth data (where k is a natural number) read from the memory cell at a kth timing different from the first timing and the second timing.
4 more elements
A semiconductor memory device comprising:
- a memory cell array comprising a plurality of memory cells arranged in a matrix and each connected to a word line and a bit line, data in h memory cells (where h is a natural number) of the plurality of memory cells being simultaneously read from the memory cell array;
- a sense amplifier connected to the bit line to detect a voltage of the bit line;
- and
- a control circuit configured to control potentials of the word line and the bit line,
- wherein, in a read of k−1 levels (k≦n) stored in the memory cell, the control circuit, upon applying a given voltage to the word line,
- determines first data corresponding to the voltage of the bit line read at a first timing by the sense amplifier, second data corresponding to the voltage of the bit line read at a second timing by the sense amplifier, third data corresponding to the voltage of the bit line read at a third timing by the sense amplifier, and kth (where k is a natural number) data corresponding to the voltage of the bit line read at a kth timing by the sense amplifier,
- determines a number of first memory cells (less than or equal to h) included between the first data and the second data, a number of second memory cells (less than or equal to h) included between the second data and the third data, and a number of k−1th memory cells (less than or equal to h) included between the kth data and the third data, and
- determines a read level of the memory cell to be a smallest value of the first, second, . . . , k−1th numbers of memory cells or the smallest value plus an offset.
5 more elements
A semiconductor memory device comprising:
- a memory cell array comprising a plurality of memory cells arranged in a matrix and each connected to a word line and a bit line, data in h memory cells (where h is a natural number) of the plurality of memory cells being simultaneously read from the memory cell array;
- a sense amplifier connected to the bit line to detect a voltage of the bit line;
- and
- a control circuit configured to control potentials of the word line and the bit line,
- wherein, in a read of k−1 levels (k≦n) stored in the memory cell, the control circuit, upon applying a given voltage to the word line,
- determines first data corresponding to the voltage of the bit line read at a first timing by the sense amplifier, second data corresponding to the voltage of the bit line read at a second timing by the sense amplifier, third data corresponding to the voltage of the bit line read at a third timing by the sense amplifier, and kth (where k is a natural number) data corresponding to the voltage of the bit line read at a kth timing by the sense amplifier,
- determines a number of first memory cells (less than or equal to h) included between the first data and the second data, a number of second memory cells (less than or equal to h) included between the second data and the third data, and a number of k−1th memory cells (less than or equal to h) included between the kth data and the third data,
- determines a read level of the memory cell to be a smallest value of the first, second, . . . , k−1th numbers of memory cells or the smallest value plus an offset,
- reads first data from i memory cells of the h memory cells at the first timing,
- reads second data from i memory cells of the h memory cells at the second timing,
- reads third data from i memory cells of the h memory cells at the third timing, and
- reads kth data (where k is a natural number) from memory cells of the h memory cells at the kth timing.
9 more elements
Dependencies are inferred from the claim text.