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US 2014/0233308 A1Published application
Semiconductor memory device and writing method thereof
AssigneeSK hynix Inc.
InventorsTae Gyun KIM, Chi Wook AN
Life of this patent
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Abstract
A writing method of a semiconductor memory device includes applying a plurality of program voltages sequentially generated to a selected word line, and applying any one of a plurality of source selection line voltages to a source selection line when each of the plurality of program voltages is applied.
Claims20
A writing method of a semiconductor memory device, the writing method comprising:
- applying a plurality of program voltages sequentially generated to a selected word line;
- and
- applying any one of a plurality of source selection line voltages to a source selection line when each of the plurality of program voltages is applied.
A semiconductor memory device, comprising:
- a memory cell array including a plurality of memory cells and source selection transistors coupled between the plurality of memory cells and a common source line;
- and
- a peripheral circuit configured to write data in selected memory cells among the plurality of memory cells by performing a plurality of program operations,
- wherein the peripheral circuit is configured to apply any one of a plurality of source selection line voltages to the source selection transistors when each of the plurality of program operations is performed.
1 more element
A semiconductor memory device, comprising:
- a memory cell array coupled to a drain selection line, a source selection line and a plurality of word lines between the drain selection line and the source selection line;
- a word line voltage generator configured to generate a plurality of program voltages to be applied to a selected word line among the plurality of word lines during a write operation;
- and
- a first selection line voltage generator configured to generate any one of the plurality of source selection line voltages when each of the plurality of program voltages are generated,
- wherein the source selection line voltage generated by the first selection line voltage generator is applied to the source selection line.
2 more elements
A computer system including a semiconductor memory device and a central processing unit, the semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells and source selection transistors coupled between the plurality of memory cells and a common source line;
- and
- a peripheral circuit configured to write data in selected memory cells among the plurality of memory cells by performing a plurality of program operations,
- wherein the peripheral circuit is configured to apply any one of a plurality of source selection line voltages to the source selection transistors when each of the plurality of program operations is performed.
1 more element
Dependencies are inferred from the claim text.