SRAM Multiplexing Apparatus
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYi-Tzu Chen, Wei-jer Hsieh, Tsai-Hsin Lai, Ling-Fang Hsu, Hau-Tai Shieh
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Abstract
An SRAM multiplexing apparatus comprise a plurality of local multiplexers and a global multiplexer. Each local multiplexer is coupled to a memory bank. The global multiplexer has a plurality of inputs, each of which is coupled to a corresponding output of the plurality of local multiplexers. In response to a decoded address in a read operation, an input of a local multiplexer is forwarded to a corresponding input of the global multiplexer. Similarly, the decoded address allows the global multiplexer to forward the input signal to a data out port via a buffer.
Claims20
A method comprising:
- performing a first logic operation by a first sense amplifier, wherein the firs sense amplifier has a first input coupled to a first bit line of a memory bank and a second input coupled to a second bit line of the memory bank;
- in response to a decoded address of a read operation, selecting an output of a first multiplexer, wherein the output of the first multiplexer is coupled to a second multiplexer and an input of the first multiplexer is coupled to the first sense amplifier;
- and
- in response to the decoded address, selecting, by the second multiplexer, an input from a plurality of inputs coupled to the second multiplexer.
A method comprising:
- receiving, by a plurality of first level multiplexers, a first control signal derived from a decoded address, wherein the plurality of first level multiplexers, each of which is coupled to a memory bank;
- in response to the first control signal, each first level multiplexer selecting an input from a plurality of inputs sent from a corresponding memory bank;
- receiving, by a second level multiplexer, a second control signal derived from the decoded address, wherein the second level multiplexer is coupled to the plurality of first level multiplexers;
- and
- sending an output signal from the second level multiplexer to a buffer.
A method comprising:
- receiving a decoded address during a read operation;
- performing a first multiplexing operation by selecting one memory cell output from a plurality of memory cells based on the decoded address;
- and
- performing a second multiplexing operation by selecting an input corresponding to a selected input at the first multiplexing operation based upon the decoded address.
Dependencies are inferred from the claim text.