Resistive switching for non volatile memory device using an integrated breakdown element
AssigneeThe Regents of the University of Michigan
InventorsWei Lu, Sung Hyun Jo
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Abstract
A method of suppressing propagation of leakage current in an array of switching devices. The method includes providing a dielectric breakdown element integrally and serially connected to a switching element within each of the switching device. A read voltage (for example) is applied to a selected cell. The propagation of leakage current is suppressed by each of the dielectric breakdown element in unselected cells in the array. The read voltage is sufficient to cause breakdown in the selected cells but insufficient to cause breakdown in the serially connected, unselected cells in a specific embodiment. Methods to fabricate of such devices and to program, to erase and to read the device are provided.
Claims5
A method for reading a memory cell, comprising:
- providing a plurality of memory cells in an array, each of the memory cells comprising a switching device and an integrated breakdown element, the integrated breakdown element being serially connected to the switching device;
- applying a write voltage to a selected memory cell within the plurality of memory cells to cause the selected memory cell to be in a write state;
- and
- applying a read voltage to the selected memory cell, the read voltage being less than a sum of a plurality of breakdown voltages and being less than the write voltage, the plurality of breakdown voltages being respectively associated with a plurality of the integrated breakdown elements forming a sneak path among the memory cells associated with the plurality of integrated breakdown elements.
A method for writing a memory cell, comprising
- providing an array of memory cells, each of the memory cells comprising a switching device and an integrated breakdown element, the integrated breakdown element being serially connected to the switching device;
- and
- applying a write voltage to a selected memory cell to cause the memory cell to be in a write state, the write voltage being no smaller than twice a break down voltage of the breakdown element and being no smaller than a first write voltage of the switching device of the selected memory cell.
A method for erasing a memory cell, comprising
- providing an array of memory cells, each of the memory cell comprising a switching device and an integrated breakdown element, the integrated breakdown element being serially connected to the switching device;
- selecting a memory cell from the array of memory cells to be erased, the selected memory cell being in a write state;
- and
- applying an erase voltage to the selected memory cell during an erase cycle to cause the selected memory cell to change from the write state to an erase state, the magnitude of the erase voltage being greater than the magnitude of a breakdown voltage of the breakdown element of the selected memory cell and being no smaller than the magnitude of a first erase voltage of the switching device of the selected memory cell.
Dependencies are inferred from the claim text.