Apparatus and methods for forming a memory cell using charge monitoring

An apparatus comprising:

• a memory cell;
• a capacitor;
• a comparator with a first input coupled to the capacitor, a second input coupled to a reference voltage node and an output;
• a transistor coupled to the capacitor and to the memory cell;
• and
• control logic coupled to the output of the comparator, wherein said control logic is configured to adjust a voltage applied to a gate of the transistor based on the output of the comparator to form the memory cell.

An apparatus comprising:

• a memory cell;
• a capacitor;
• a transistor coupled to the memory cell and to the capacitor;
• an analog to digital converter (ADC) coupled to the capacitor, the ADC having an output based on a voltage of the capacitor;
• and
• control logic coupled to the output of the ADC, wherein said control logic is configured to adjust a voltage applied to a gate of the transistor based on the output of the ADC to form the memory cell.

A method of forming a memory cell comprising:

• charging a capacitor;
• coupling the charged capacitor to the memory cell;
• monitoring a forming charge applied to the memory cell responsive to coupling the charged capacitor to the memory cell;
• and
• decoupling the charged capacitor from the memory cell responsive to the monitoring.

A method for forming a memory cell comprising:

• charging a capacitor;
• discharging the capacitor through a transistor coupled to a memory cell;
• monitoring the charge that was discharged to the memory cell;
• and
• determining if the charge is sufficient to form the memory cell.