3d semiconductor device

A semiconductor integrated circuit, comprising:

• a chip pad;
• a memory cell array;
• a decoder configured to select a cell of the memory cell array;
• and
• a first information path extending between the chip pad and at least one of the memory cell array and the decoder;
• a through substrate via extending from a chip terminal other than the chip pad to a node of the first information path to form a second information path comprising a portion of the first information path and the through substrate via;
• a chip identification programmable circuit having a chip identification output identifying the semiconductor integrated circuit as a master chip or a slave chip;
• a selection circuit responsive to the chip identification output identifying the integrated circuit as a master chip to select the first information path, including the chip pad, as a communication path for an external communication with respect to the integrated circuit, and responsive to the chip identification output identifying the integrated circuit as a slave chip to select the second information path, including the through substrate via, as a communication path for the external communication with respect to the integrated circuit.

A semiconductor package comprising:

• at least a first chip stacked with a second chip, the first and second chip having identical circuit designs, each of the first and second chips comprising:
• a chip pad;
• a memory cell array;
• a decoder configured to select a cell of the memory array;
• and
• a first information path extending between the chip pad and at least one of the memory cell array and the decoder;
• a through substrate via extending from a chip terminal other than the chip pad to a node of the first information path to form a second information path comprising a portion of the information path and the through substrate via;
• and
• a chip identification programmable circuit having a chip identification output to identify the chip as a master chip or a slave chip;
• wherein the through substrate via of the first chip is connected to the through substrate via of the second chip to comprise a through substrate via connection of the semiconductor package,
• wherein the chip identification programmable circuit of the first chip identifies the first chip as a master chip,
• wherein the chip identification programmable circuit of the second chip identifies the second chip as a slave chip, wherein the slave chip is responsive to the master chip due to signals received by the through substrate via connection.

A semiconductor device comprising:

• a first semiconductor chip having a first through substrate via and a via pad connected to the first through substrate via at a first surface of the first semiconductor chip;
• a second semiconductor chip having a second through substrate via extending above a first surface of the second chip a first distance;
• and
• a bump,
• wherein the first semiconductor chip is stacked with the second semiconductor chip, the first surface of the first semiconductor chip facing the first surface of the second semiconductor chip;
• wherein the bump and via pad of the first semiconductor chip connect the first through substrate via to the second through substrate via, and
• wherein the height of the bump is less than the first distance.