Liquid crystal display device

A liquid crystal display device comprising:

• a plurality of pixels individually provided at an intersecting portion at which a plurality of pairs of two column data lines intersects with a plurality of row scanning lines,
• each of the pixels individually including:
• a display element configured to have liquid crystals filled and sealed between a pixel electrode and a common electrode opposing to each other;
• a first switching unit configured to sample normal subframe data for displaying each frame of a video signal in a plurality of subframes having a display period shorter than one frame period of the video signal through one column data line of a pair of the two column data lines;
• a second switching unit configured to sample reverse subframe data in relation of inverted logical value with the normal subframe data through the other column data line of a pair of the two column data lines;
• a first signal holding unit
• formed of first and second inverters in which an output terminal of one inverter is connected to an input terminal of the other inverter,
• configured to store the normal subframe data and the reverse subframe data sampled by the first switching unit and the second switching unit individually, and
• configured to form a first static random access memory together with the first switching unit and the second switching unit;
• a third switching unit configured to output the normal subframe data from a connecting point between the first signal holding unit and the first switching unit;
• a fourth switching unit configured to output the reverse subframe data from a connecting point between the first signal holding unit and the second switching unit;
• and
• a second signal holding unit
• formed of third and fourth inverters in which an output terminal of one inverter is connected to an input terminal of the other inverter, in which stored content is rewritten with the normal subframe data and the reverse subframe data stored in the first signal holding unit supplied through the third switching unit and the fourth switching unit,
• configured to apply output data to the pixel electrode, and
• configured to form a second static random access memory together with the third switching unit and the fourth switching unit, wherein:
• in the first and second inverters, a driving force of the second inverter of which output terminal is connected to the first switching unit is set smaller than a driving force of the first inverter of which output terminal is connected to the second switching unit, and the driving forces of the first and second inverters are set larger than driving forces of the third and fourth inverters;
• and
• a pixel control unit performs, for each individual subframe, operations of:
• after writing into all the plurality of pixels, which configures an image display unit, by repeatedly writing the normal subframe data and the reverse subframe data into the first signal holding unit for each of the pixels in units of rows;
• turning on the third switching units and the fourth switching units of all of the plurality of pixels with a trigger pulse;
• and
• rewriting the stored content in the second signal holding units of the plurality of pixels with the normal subframe data and the reverse subframe data that are held in the first signal holding unit.

A liquid crystal display device comprising:

• a plurality of pixels individually provided at an intersecting portion at which a plurality of column data lines intersects with a plurality of row scanning lines,
• each of the pixels individually including:
• a display element configured to have liquid crystals filled and sealed between a pixel electrode and a common electrode opposite to each other;
• a first switching unit
• formed of a single transistor, and
• configured to sample subframe data for displaying every frame of a video signal in a plurality of subframes having a display period shorter than one frame period of the video signal through the column data line;
• a first signal holding unit,
• formed of first and second inverters in which an output terminal of one inverter is connected to an input terminal of the other inverter, and stores the subframe data sampled by the first switching unit, and
• forming a first static random access memory together with the first switching unit;
• a second switching unit formed of a single transistor, and configured to output the subframe data stored in the first signal holding unit;
• and
• a second signal holding unit
• formed of third and fourth inverters, in which stored content is rewritten with the subframe data stored in the first signal holding unit supplied through the second switching unit, output data is applied to the pixel electrode, and an output terminal of one inverter is connected to an input terminal of the other inverter, and
• forms a second static random access memory together with the second switching unit, wherein
• in the first and second inverters, a driving force of the second inverter of which output terminal is connected to the first switching unit is set smaller than a driving force of the first inverter and set smaller than a driving force of the transistor forming the first switching unit;
• in the third and fourth inverters, a driving force of the fourth inverter of which output terminal is connected to the second switching unit is set smaller than a driving force of the third inverter and set smaller than a driving force of the transistor forming the second switching unit, and the driving force of the first inverter is set larger than the driving force of the fourth inverter;
• and
• a pixel control unit configured to perform, for individual subframes, the operations of:
• after writing into all of the plurality of pixels, which configures an image display unit, by repeatedly writing the subframe data to the first signal holding unit for the individual pixels in units of rows;
• turning on the second switching units in all of the plurality of pixels with a trigger pulse;
• and
• rewriting the stored content in the second signal holding units of the plurality of pixels with the subframe data stored in the first signal holding unit.