Voltage generator, switch and data converter circuits

A digital-to-analog converter circuit, comprising:

• a resistor network including a plurality of interconnected resistors;
• a switch network connected to the resistor network, the switch network including a plurality of switch circuits, each having an NMOS and a PMOS switch transistor;
• and
• a voltage generator to generate a drive voltage at an output terminal for driving a gate of at least one of the NMOS or PMOS switch transistors of at least one of the switch circuits, the voltage generator including:
• a first pair of transistors, having connected control terminals and being connected to a second NMOS transistor and a first resistor;
• and
• a second pair of transistors, having connected control terminals and being connected to a second PMOS transistor, a second resistor and the first pair of transistors,
• wherein a ratio of the second NMOS transistor's width-to-length ratio to the second PMOS transistor's width-to-length ratio is substantially equal to a ratio of the switch circuit NMOS transistor's width-to-length ratio to the switch circuit PMOS transistor's width-to-length ratio.

A voltage generator circuit to generate a drive voltage, the voltage generator circuit comprising:

• a first pair of transistors, having connected control terminals and being connected to an NMOS transistor and a first resistor;
• and
• a second pair of transistors, having connected control terminals and being connected to a PMOS transistor, a second resistor and the first pair of transistors,
• wherein a gate of one of the NMOS or PMOS transistors is connected to an output terminal of the voltage generator circuit, and the generated drive voltage is a gate-to-source voltage of the one of the NMOS or PMOS transistors.

A switching circuit, comprising:

• a switch network connected to a resistor network, the switch network including a plurality of switch circuits, each having an NMOS and a PMOS switch transistor;
• and
• a voltage generator to generate a drive voltage at an output terminal for driving a gate of at least one of the NMOS or PMOS switch transistors of at least one of the switch circuits, the voltage generator including:
• a first pair of bipolar transistors, having connected bases and being connected to a second NMOS transistor and a first resistor;
• and
• a second pair of bipolar transistors, having connected bases and being connected to a second PMOS transistor, a second resistor and the first pair of transistors.

A switching circuit, comprising:

• a switch network connected to a resistor network, the switch network including a plurality of switch circuits, each having an NMOS and a PMOS switch transistor;
• and
• a voltage generator to generate a drive voltage at an output terminal for driving a gate of at least one of the NMOS or PMOS switch transistors of at least one of the switch circuits, the voltage generator including:
• a first pair of transistors, having connected control terminals and being connected to a second NMOS transistor and a first resistor;
• and
• a second pair of transistors, having connected control terminals and being connected to a second PMOS transistor, a second resistor and the first pair of transistors,
• wherein a ratio of the second NMOS transistor's width-to-length ratio to the second PMOS transistor's width-to-length ratio is substantially equal to a ratio of the switch circuit NMOS transistor's width-to-length ratio to the switch circuit PMOS transistor's width-to-length ratio.

A voltage generator circuit, comprising:

• a pair of NMOS transistors, having connected gates and each being connected at a source to a respective one of a third NMOS transistor or a first resistor;
• and
• a pair of PMOS transistors, having connected gates and each being connected at a source to a respective one of a third PMOS transistor or a second resistor,
• wherein the pair of NMOS transistors is connected at drains to drains of the pair of PMOS transistors.