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US 2014/0232450 A1Published application
Circuit For Canceling Errors Caused By Parasitic And Device-Intrinsic Resistances In Temperature Dependent Integrated Circuits
AssigneeRobert Bosch GmbH
InventorsChristoph Lang, Crist Lu
Life of this patent
Estimating the term…
Abstract
In one embodiment, a circuit includes at least one transistor with a base and collector being electrically connected to a ground, and at least one current source being configured to apply four different currents (A, B, C, and D) to the emitter. A sum of the currents A and C are substantially equivalent to a sum of the currents B and D, or a sum of the currents A and D are substantially equivalent to a sum of the currents B and C. The circuit outputs first, second, third, and fourth voltage potentials between the emitter and the base during application of the currents A, B, C, and D, respectively.
Claims25
A circuit comprising:
- at least one diode;
- at least one current source being configured to apply four different currents (A, B, C, and D) to the diode, the at least one current source being configured to produce the four different currents with either:
- a sum of the current A and the current C being substantially equivalent to a sum of the current B and the current D;
- or
- a sum of the current A and the current D being substantially equivalent to a sum of the current B and the current C;
- and
- the circuit being configured to output:
- a first voltage across the at least one diode during application of the current A to the at least one diode;
- a second voltage across the at least one diode during application of the current B to the at least one diode;
- a third voltage across the at least one diode during application of the current C to the at least one diode;
- and
- a fourth voltage across the at least one diode during application of the current D to the at least one diode.
9 more elements
A circuit comprising:
- at least one transistor with a base, a collector, and an emitter;
- at least one current source being configured to apply four different currents (A, B, C, and D) to the emitter of the at least one transistor, the at least one current source being configured to produce the four different currents with either:
- a sum of the current A and the current C being substantially equivalent to a sum of the current B and the current D;
- or
- a sum of the current A and the current D being substantially equivalent to a sum of the current B and the current C;
- and
- the circuit being configured to output:
- a first voltage potential between the emitter of the at least one transistor and the base during application of the current A to the emitter of the at least one transistor;
- a second voltage potential between the emitter of the at least one transistor and the base during application of the current B to the emitter of the at least one transistor;
- a third voltage potential between the emitter of the at least one transistor and the base during application of the current C to the emitter of the at least one transistor;
- and
- a fourth voltage potential between the emitter of the at least one transistor and the base during application of the current D to the emitter of the at least one transistor.
9 more elements
A circuit comprising:
- a parasitic resistance system including at least one parasitic resistance device with a base, a collector, and an emitter;
- and
- at least one current source configured to apply four different currents (A, B, C, and D) to at least one emitter of the parasitic resistance system to generate an emitter-base voltage potential,
- wherein either (i) a sum of the current A and the current C is substantially equivalent to a sum of the current B and the current D, or (ii) a sum of the current A and the current D is substantially equivalent to a sum of the current B and the current C, and
- wherein the circuit is configured to (i) generate a first emitter-base voltage potential during application of the current A, (ii) generate a second emitter-base voltage potential during application of the current B, (iii) generate a third emitter-base voltage potential during application of the current C, (iv) generate a fourth emitter-base voltage potential during application of the current D, and (v) generate an output associated with a temperature of the transistor set based upon the first emitter-base voltage potential, the second emitter-base voltage potential, the third emitter-base voltage potential, and the fourth emitter-base voltage potential.
2 more elements
Dependencies are inferred from the claim text.