Level shift circuit
AssigneeSeiko Instruments Inc.
InventorsKosuke TAKADA, Atsushi IGARASHI
Life of this patent
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Abstract
There is provided a level shift circuit free from malfunction. The level shift circuit converts a signal of a first power supply voltage of a first supply terminal, which is supplied to an input terminal, into a signal of a second power supply voltage of a second supply terminal and outputs the converted signal to an output terminal. The level shift circuit has a control circuit that detects when the first power supply voltage reduces below a predetermined voltage. The voltage of the output terminal of the level shift circuit is fixed to the second power supply voltage or a ground voltage according to a detection signal of the control circuit.
Claims6
A level shift circuit adapted to convert a signal of a first power supply voltage of a first supply terminal, which is supplied to an input terminal, into a signal of a second power supply voltage of a second supply terminal and outputs the converted signal to an output terminal, the level shift circuit comprising;
- a control circuit which detects when the first power supply voltage reduces below a predetermined voltage,
- wherein a voltage of the output terminal of the level shift circuit is fixed to the second power supply voltage or a ground voltage according to a detection signal of the control circuit.
A level shift circuit mounted on a semiconductor device, comprising:
- a signal processing circuit and a control circuit,
- wherein the signal processing circuit comprises:
- a first NMOS transistor having a source thereof connected to a ground terminal and a drain thereof connected to a first internal node;
- a second NMOS transistor having a source thereof connected to a ground terminal and a drain thereof connected to a second internal node;
- a first inverter having an input terminal thereof connected to an input terminal of the signal processing circuit and a gate of the second NMOS transistor, an output terminal thereof connected to a gate of the first NMOS transistor, and a supply terminal thereof connected to a first supply terminal;
- a first switch which is controlled by a signal of a first control signal terminal of the signal processing circuit and which is provided between the first internal node and a ground terminal;
- a second switch which is controlled by a signal of a second control signal terminal of the signal processing circuit and which is provided between an output terminal of the signal processing circuit and the second internal node;
- a first PMOS transistor having a gate thereof connected to the output terminal of the signal processing circuit, a source thereof connected to a second supply terminal, and a drain thereof connected to the first internal node;
- and
- a second PMOS transistor having a gate thereof connected to the first internal node, a source thereof connected to the second supply terminal, and a drain thereof connected to the output terminal of the signal processing circuit;
- and
- the control circuit comprises:
- a voltage detector circuit which has an input terminal thereof connected to the first supply terminal and which detects when a first power supply voltage becomes a voltage of the total of a minimum operating power supply voltage and a predetermined voltage;
- and
- a second inverter having an input terminal thereof connected to an output terminal of the voltage detector circuit and the first control signal terminal, an output terminal thereof connected to the second control signal terminal, and a supply terminal thereof connected to the second supply terminal.
Dependencies are inferred from the claim text.