Circuit element including a layer of a stress-creating material providing a variable stress and method for the formation thereof

A circuit, comprising:

• a current mirror circuit, said current mirror circuit comprising a first transistor in an input current path of said current mirror circuit and a second transistor in an output current path of said current mirror circuit, wherein each of said first and second transistors comprises a source region, a drain region, a channel region and a gate electrode, and at least one of said first transistor and said second transistor comprises a layer of a stress-creating material, said stress-creating material providing a stress that is variable in response to a signal acting on said stress-creating creating material, said stress-creating material having a stress hysteresis wherein said stress provided in response to said signal is at least partially maintained after removal of said signal, wherein said layer of stress-creating material is arranged to provide a stress in at least said channel region of the transistor wherein it is provided, said stress being variable in response to said signal acting on said stress-creating material;
• and
• a calibration circuit for calibrating said current mirror circuit, said calibrating comprising detecting a current difference between a current flowing through said input current path and a ratio between a current flowing though said output current path and a multiplication factor and applying a signal to said stress-creating material in the at least one of the first transistor and the second transistor in response to the detected current difference, the application of the signal reducing the current difference.

An inverter, comprising:

• a pull-up transistor and a pull-down transistor, said pull-up transistor and said pull-down transistor being electrically connected in series between a high voltage power supply terminal and a low voltage power supply terminal;
• an input terminal electrically connected to said pull-up transistor and said pull-down transistor, said pull-up transistor being switchable to an off-state by applying a high voltage to said input terminal and to an on-state by applying a low voltage to said input terminal, said pull-down transistor being switchable to an on-state by applying a high voltage to said input terminal and to an off-state by applying a low voltage to said input terminal;
• wherein said pull-up transistor comprises a first layer of stress-creating material providing a variable stress in a channel region of said pull-up transistor that is variable in response to said voltage applied to said input terminal, wherein said variable stress increases a mobility of charge carriers in said channel region of said pull-up transistor obtained in the on-state of said pull-up transistor compared to a mobility of charge carriers in said channel region of said pull-up transistor obtained in the off-state of said pull-up transistor;
• wherein said pull-down transistor comprises a second layer of a stress-creating material providing a stress in a channel region of said pull-down transistor that is variable in response to said voltage applied to said input terminal, wherein said variable stress increases a mobility of charge carriers in said channel region of said pull-down transistor obtained in the on-state of said pull-down transistor compared to a mobility of charge carriers in said channel region of said pull-down transistor obtained in the off-state of said pull-down transistor.

A memory cell, comprising:

• a first transistor, said first transistor comprising a source region, a drain region, a channel region, a gate electrode, a layer of stress-creating material, said stress-creating material providing a stress in said channel region that is variable in response to an electric field applied to said layer of stress-creating material, said stress-creating material having a stress hysteresis, wherein the stress provided in response to said electric field is at least partially maintained after removal of said electric field, and at least one stress-control electrode provided adjacent said layer of stress-creating material;
• a read terminal electrically connected to said gate electrode of said first transistor;
• and
• a write terminal electrically connected to one of said at least one stress-control electrode of said first transistor.

A method, comprising:

• providing a substrate comprising a semiconductor material;
• forming a gate insulation layer and a gate electrode over said semiconductor material;
• forming a source region and a drain region in said semiconductor material adjacent said gate electrode, a portion of said semiconductor material below said gate electrode providing a channel region;
• and
• forming a layer of a stress-creating material over said source region, said drain region and said gate electrode, said stress-creating material providing a stress in said channel region that is variable in response to a signal acting on said stress-creating material.