Method and apparatus for hybrid chip-level voltage scaling
AssigneeQUALCOMM Incorporated
InventorsAjay Cheriyan, Rajesh Joshi, Madan Krishnappa
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Abstract
Various aspects of a power management approach for a system-on-a-chip (SoC) is disclosed herein. In one aspect, the approach includes implementing a power profile for supplying power to a plurality of subsystems on a shared power bus in the SoC. The power profile includes at least one adjustable parameter for controlling the supplied power during an active use state. The approach further includes detecting a power profile change trigger; modifying the power profile based on the power profile change trigger; and adjusting the supplied power during the active use state based on the modified power profile to maintain a predetermined supplied power level
Claims40
A method for power management of a system-on-a-chip (SoC), comprising:
- implementing a power profile for supplying power to a plurality of subsystems on a shared power bus, wherein the power profile comprises at least one adjustable parameter for controlling the supplied power during an active use state;
- detecting a power profile change trigger;
- modifying the power profile based on the power profile change trigger;
- and
- adjusting the supplied power during the active use state based on the modified power profile to maintain a predetermined supplied power level.
An apparatus for hybrid chip-level voltage scaling, comprising:
- means for implementing a power profile for supplying power to a plurality of subsystems on a shared power bus, wherein the power profile comprises at least one adjustable parameter for controlling the supplied power during an active use state;
- means for detecting a power profile change trigger;
- means for modifying the power profile based on the power profile change trigger;
- and
- means for adjusting the supplied power during the active use state based on the modified power profile to maintain a predetermined supplied power level.
A processor-readable storage medium comprising instructions stored thereon, which when executed by a processor, causes the processor to:
- implement a power profile for supplying power to a plurality of subsystems on a shared power bus, wherein the power profile comprises at least one adjustable parameter for controlling the supplied power during an active use state;
- detect a power profile change trigger;
- modify the power profile based on the power profile change trigger;
- and
- adjust the supplied power during the active use state based on the modified power profile to maintain a predetermined supplied power level.
An apparatus for hybrid chip-level voltage scaling, comprising:
- at least one processor;
- and
- a memory coupled to the at least one processor, wherein the memory is configured to cause the at least one processor to:
- implement a power profile for supplying power to a plurality of subsystems on a shared power bus, wherein the power profile comprises at least one adjustable parameter for controlling the supplied power during an active use state;
- detect a power profile change trigger;
- modify the power profile based on the power profile change trigger;
- and
- adjust the supplied power during the active use state based on the modified power profile to maintain a predetermined supplied power level.
Dependencies are inferred from the claim text.