Memory circuits and routing of conductive layers thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon Jhy LIAW
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Abstract
A memory circuit memory circuit comprises at least one memory cell for storing a datum. The memory cell is coupled with a word line, a bit line, a bit line bar, a first voltage line, and a second voltage line. A first conductive layer comprising a first landing pad and a second landing pad is arranged at a first level. A second conductive layer is coupled to the first conductive layer and arranged at a second level different from the first level. The second conductive layer is routed to define the first voltage line and the second voltage line. A third conductive layer is coupled to the second conductive layer and arranged at a third level different from the first level and the second level. The third conductive layer is routed to define the word line.
Claims20
A memory circuit, comprising:
- at least one memory cell for storing a datum, the memory cell being coupled with a word line, a bit line, a bit line bar, a first voltage line, and a second voltage line;
- a first conductive layer arranged at a first level, the first conductive layer comprising a first landing pad and a second landing pad;
- a second conductive layer coupled to the first conductive layer and arranged at a second level different from the first level, the second conductive layer being routed to define the first voltage line and the second voltage line;
- and
- a third conductive layer coupled to the second conductive layer and arranged at a third level different from the first level and the second level, the third conductive layer being routed to define the word line,
- wherein the bit line is disposed adjacent to the first landing pad and the bit line bar is disposed adjacent to the second landing pad.
The memory circuit of claim Error! Reference source not found, wherein the first conductive layer is routed for the bit line and the bit line bar, the second conductive layer is over the first conductive layer, the second conductive layer is routed for the first voltage line and the second voltage line, and the third conductive layer is over the second conductive layer.
The memory circuit of claim Error! Reference source not found, wherein the first voltage line is a Vdd line and the second voltage line is a Vss line, and the word line is substantially orthogonal to the Vss line.
The memory circuit of claim Error! Reference source not found, wherein a width of the third conductive layer for the word line within the memory cell is about 50% or more of a width of a short side of the memory cell.
A memory circuit, comprising:
- at least one memory cell for storing a datum, the memory cell being coupled with a word line, a bit line, a bit line bar, a first voltage line, and a second voltage line;
- a first metal layer arranged at a first level, the first metal layer comprising a first landing pad and a second landing pad;
- a second metal layer coupled to the first metal layer and arranged at a second level different from the first level, the second conductive layer being routed to define the first voltage line and the second voltage line;
- and
- a third metal layer coupled to the second conductive layer and arranged over the second metal layer, the third conductive layer being routed to define the word line,
- wherein the bit line is disposed adjacent to the first landing pad and the bit line bar is disposed adjacent to the second landing pad.
A memory circuit, comprising:
- at least one memory cell for storing a datum, the memory cell being coupled with a word line, a bit line, a bit line bar, a first voltage line, and a second voltage line;
- a first layer defining electrical connections within the memory cell, the first layer comprising a first landing pad and a second landing pad;
- a second layer coupled to the first layer, the second layer being routed to define the first voltage line;
- and
- a third layer coupled to the second layer,
- wherein the bit line is disposed adjacent to the first landing pad and the bit line bar is disposed adjacent to the second landing pad.
Dependencies are inferred from the claim text.