Stacked package, method of fabricating stacked package, and method of mounting stacked package fabricated by the method

A stacked semiconductor package, comprising:

• an upper semiconductor package including an upper package substrate and one or more upper semiconductor chips formed on the upper package substrate, a first surface of the upper semiconductor package substrate including first bonding pads for connecting to outside the upper semiconductor package;
• a lower semiconductor package including a lower package substrate and one or more lower semiconductor chips formed on the lower package substrate, a first surface of the lower semiconductor package substrate including second bonding pads for connecting to outside the lower semiconductor package;
• and
• inter-package bonding units electrically and physically connecting the first bonding pads to respective ones of the second bonding pads,
• wherein the inter-package bonding units include first solders having a first melting temperature in contact with first respective annealed solder paste nodes having a second melting temperature.

An inter-substrate bonding unit for electrically and physically connecting a first semiconductor substrate of a first semiconductor package to a second semiconductor substrate of a second semiconductor package, the inter-substrate bonding unit comprising:

• a first solder having a first melting temperature, the first solder connected to a bonding pad on a surface of the first semiconductor substrate;
• and
• an annealed solder paste node having a second melting temperature, the annealed solder paste node connected to a bonding pad on a surface of the second semiconductor substrate and connected to the first solder, wherein
• the annealed solder paste node has a melting temperature prior to annealing lower than the first melting temperature and lower than the second melting temperature.

A stacked semiconductor package, comprising:

• an upper semiconductor package including an upper package substrate, upper semiconductor chips formed on a top surface of the upper package substrate, and first solders formed on a bottom surface of the upper package substrate and having a first melting temperature;
• a lower semiconductor package including a lower package substrate, lower semiconductor chips formed on a top surface of the lower package substrate, and transformed solder paste nodes formed on the top surface of the lower package substrate and having a second melting temperature higher than the first melting temperature, wherein the transformed solder paste nodes are interposed between the top surface of the lower package substrate and the first solders;
• and
• second solders formed on a bottom surface of the lower package substrate and having a third melting temperature lower than the first and second melting temperature.

A stacked semiconductor package, comprising:

• a package substrate;
• semiconductor chips formed on a top surface of the package substrate;
• first solders formed on a bottom surface of the package substrate and having a first melting temperature;
• and
• transformed solder paste nodes interposed between the bottom surface of the package substrate and the first solders and having a second melting temperature higher than the first melting temperature.