Back End of the Line (BEOL) Interconnect Scheme
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChi-Liang Kuo, Tz-Jun Kuo, Hsiang-Huan Lee
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Abstract
The present disclosure relates to a method of forming a back-end-of-the-line metal interconnect layer. The method is performed by depositing one or more self-assembled monolayers on a semiconductor substrate to define a metal interconnect layer area. A metal interconnect layer having a plurality of metal structures is formed on the semiconductor substrate within the metal interconnect layer area. An inter-level dielectric layer is then formed onto the surface of the semiconductor substrate in areas between the plurality of metal structures.
Claims22
A method of forming a metal back-end-of-the-line interconnect layer, comprising:
- depositing one or more self-assembled monolayers, respectively comprising an ordered assembly of organic molecules having a head group connected to a terminal group by a molecular chain, on a semiconductor substrate to define a metal interconnect layer area;
- selectively depositing a metal interconnect layer comprising a plurality of metal structures on the semiconductor substrate within the metal interconnect layer area;
- and
- depositing an inter-level dielectric layer onto the semiconductor substrate in areas between the plurality of metal structures.
(canceled)
A method of forming a back-end-of-the-line (BEOL) metal interconnect layer, comprising:
- selectively depositing a first self-assembled monolayer (SAM) on an underlying first inter-level dielectric layer located on a substrate;
- selectively depositing a second self-assembled monolayer (SAM) on an underlying metal interconnect layer located on the substrate;
- selectively exposing the first SAM or the second SAM to radiation, wherein the radiation degrades a portion of the first SAM or the second SAM;
- removing the degraded portion of the first SAM or the second SAM;
- electrolessly plating a metal and an alloy dopant to form a first metal interconnect layer comprising one or more metal structures at removed areas of the first SAM or the second SAM;
- selectively forming a second inter-level dielectric layer onto the substrate in areas between the plurality of metal structures;
- and
- annealing the substrate after forming the second inter-level dielectric layer, wherein annealing the substrate forms a self-forming barrier layer between the plurality of metal structures and second inter-level dielectric layer.
15-20. (canceled)
A method of forming a metal back-end-of-the-line interconnect layer, comprising:
- depositing a plurality of self-assembled monolayers onto a first inter-level dielectric (ILD) layer disposed over a semiconductor substrate to define a metal interconnect layer area;
- selectively depositing a metal interconnect layer comprising a plurality of metal structures on one of the plurality of self-assembled monolayers within the metal interconnect layer area;
- depositing a second inter-level dielectric layer over the semiconductor substrate in areas between the plurality of metal structures;
- and
- performing an anneal process after forming the second inter-level dielectric layer to form a self-forming barrier layer between the plurality of metal structures and the second inter-level dielectric layer.
Dependencies are inferred from the claim text.