Wiring board and method for manufacturing the same

A semiconductor device, comprising:

• a semiconductor chip;
• and
• a wiring board formed on the semiconductor chip,
• wherein the wiring board comprises a resin insulation layer, a plurality of conductive patterns formed on the resin insulation layer, a plurality of via conductors connected to the plurality of conductive patterns, respectively, and a rewiring structures formed on the semiconductor chip and connecting the plurality of via conductors and a plurality of electrode pads of the semiconductor chip respectively, the plurality of conductive patterns is positioned to fan in or out with respect to the plurality of electrode pads, and each of the via conductors has a side surface extending through the resin insulation layer such that the side surface has a bent portion which changes an inclination of the side surface in a depth direction of each of the via conductors.

A method for manufacturing a semiconductor device, comprising:

• forming a first resin insulation layer on a semiconductor chip;
• forming a plurality of first conductive patterns on the first resin insulation layer;
• forming a plurality of second resin insulation layer on the first conductive patterns and the first resin insulation layer;
• forming in the second resin insulation layer a plurality of opening portions extending to the plurality of first conductive patterns respectively such that each of the opening portions has a side wall having a bent portion which changes an inclination of the side surface in a depth direction of each of the opening portions;
• forming in the plurality of opening portions of the second resin insulation layer a plurality of via conductors extending to the plurality of first conductive patterns such that each of the via conductors has a side surface having a bent portion which changes an inclination of the side surface in a depth direction of each of the via conductors;
• and
• forming a plurality of second conductive patterns on the second resin insulation layer such that the second conductive patterns is formed on the plurality of via conductors respectively and positioned to fan in or out with respect to a plurality of electrode pads of the semiconductor chip.