US 2014/0231982 A1Published application

Semiconductor device and manufacturing method thereof

AssigneeFuji Electric Co., Ltd.

InventorShogo OGAWA

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Abstract

A circuit assembly is disclosed which includes first and second substrates disposed on a heat dissipation base, and first and second semiconductor elements mounted on the first and second substrates. The first and second substrates are wired together, and three main electrode terminals are provided when the first and second semiconductor elements are connected in series, while two main electrode terminals are provided when the first and second semiconductor element are connected in parallel. In both cases, the circuit assembly is covered with a common exterior case so that one portion of each main electrode terminal or one portion of each main electrode terminal is exposed. Parts used in the circuit assembly are shared, and by changing the wiring between the first and second substrates, semiconductor modules with different functions are realized at low cost.

Claims10

Dependent claims

A semiconductor device, comprising:

a heat dissipation base;
a first substrate, disposed on the heat dissipation base, which has a first conductor pattern;
a second substrate, disposed on the heat dissipation base, which has a second conductor pattern;
a first semiconductor element, disposed on the first substrate, which has on the first conductor pattern a first collector terminal and a first emitter terminal;
a second semiconductor element, disposed on the second substrate, which has on the second conductor pattern a second collector terminal and a second emitter terminal;
a plurality of electrode terminals, wherein
in a first case in which the first emitter terminal and the second collector terminal are wired together, different ones of the electrode terminals are connected to the first collector terminal, the second emitter terminal, and the second collector terminal, and
in a second case in which the first collector terminal and the second collector terminal are wired together and the first emitter terminal and the second emitter terminal are wired together, different ones of the electrode terminals are connected to the first collector terminal and the second emitter terminal;
and
a common exterior case which covers the heat dissipation base with one portion of each of the connected electrode terminals exposed in both the first case and second case.

7 more elements

A semiconductor manufacturing method, comprising:

a step of disposing on a heat dissipation base a first substrate having a first conductor pattern;
a step of disposing on the heat dissipation base a second substrate having a second conductor pattern;
a step of disposing on the first substrate a first semiconductor element having a first emitter terminal and a first collector terminal on the first conductor pattern;
a step of disposing on the second substrate a second semiconductor element having a second emitter terminal and a second collector terminal on the second conductor pattern;
a step of wiring the first emitter terminal and second collector terminal together, or wiring the first collector terminal and second collector terminal together, and wiring the first emitter terminal and second emitter terminal together;
a step of connecting a plurality of electrode terminals, one each, to the first collector terminal, second emitter terminal, and second collector terminal in a first case in which the first emitter terminal and second collector terminal are wired together, and one each, to the first collector terminal and second emitter terminal in a second case in which the first collector terminal and second collector terminal are wired together, and the first emitter terminal and second emitter terminal are wired together;
and
a step of covering the heat dissipation base with a common exterior case, with one portion of each of the connected electrode terminals exposed, in both the first case and second case.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/220,318Filed 20 Mar 2014
Priority: JP 2011-21651230 Sep 2011
Published: 21 Aug 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification19 codes

H10W 72/00
Interconnections or connectors in packages
H10W 40/00
Arrangements for thermal protection or thermal control
H10W 40/10
Arrangements for thermal protection or thermal control: arrangements for heating
H10W 40/255
Characterised by their materials: having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates