Semiconductor packages with low stand-off interconnections between chips
OwnerNavas Khan Oratti Kalandar, Chee Seng Foong +1inventors
InventorsNavas Khan Oratti Kalandar, Chee Seng Foong, Kesvakumar V.C. Muniandy
Life of this patent
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Abstract
A method of forming a semiconductor package includes providing a support and a first semiconductor die, each having first and second main surfaces. The second main surface of the first die is disposed on the first main surface of the support. Stud bumps are formed on the first main surface of the first die. A surface of a second semiconductor die is bonded to the stud bumps. The first main surface of the first die is wire bonded to the first main surface of the support. The first and second dies, the stud bumps, the bond wire, and at least a portion of the first main surface of the support are encapsulated with a mold compound.
Claims17
A method of forming a semiconductor package, the method comprising:
- providing a support having opposing first and second main surfaces and a first semiconductor die having opposing first and second main surfaces, the second main surface of the first semiconductor die being disposed on the first main surface of the support;
- forming one or more metal stud bumps on the first main surface of the first semiconductor die;
- bonding a surface of a second semiconductor die to the one or more stud bumps, the stud bumps providing an electrical connection between the first and second semiconductor dies, wherein the bonding of the second semiconductor die to the one or more stud bumps is performed by one of thermo-compression or thermosonic bonding;
- wire bonding the first main surface of the first semiconductor die to the first main surface of the support with at least one wire to electrically connect the first semiconductor die and the support;
- and
- encapsulating the first and second semiconductor dies, the one or more stud bumps, the at least one wire, and at least a portion of the first main surface of the support with a mold compound.
(canceled)
A semiconductor package, comprising:
- a support having opposing first and second main surfaces;
- a first semiconductor die having opposing first and second main surfaces, the second main surface of the first semiconductor die being disposed on the first main surface of the support;
- at least one wire having a first end bonded to the first main surface of the first semiconductor die and a second end bonded to the first main surface of the support, the at least one wire providing an electrical connection between the first semiconductor die and the support;
- one or more metal stud bumps formed on the first main surface of the first semiconductor die;
- a second semiconductor die having opposing first and second main surfaces, a portion of the second main surface of the second semiconductor die being bonded to the one or more stud bumps using one of thermo-compression or thermosonic bonding, the one or more stud bumps providing an electrical connection between the first and second semiconductor dies;
- and
- a mold compound disposed on the first main surface of the support and encapsulating the first and second semiconductor dies, the at least one wire, and the one or more stud bumps.
Dependencies are inferred from the claim text.