Transistors with isolation regions

A transistor device, comprising:

• a source, a gate, and a drain;
• a III-N semiconductor material which includes a gate region between the source and the drain;
• a plurality of channel access regions in the III-N semiconductor material that are between the source and the gate and between the drain and the gate, respectively;
• a channel in the III-N semiconductor material;
• and
• a plurality of isolation regions in or near a region of the III-N semiconductor material which has a high electric field or is at a low electric potential during device operation, the plurality of isolation regions serving to improve the efficiency of hole collection from the III-N semiconductor material;
• wherein
• each of the plurality of isolation regions has a width, and a sum of the widths of the isolation regions is between 10% and 90% a width of the source.

A semiconductor device, comprising:

• a III-N semiconductor material;
• a conductive channel in the III-N semiconductor material;
• a first electrode, a second electrode, and a gate, wherein gate is between the first and second electrodes, and the III-N semiconductor material includes a gate region between the first and second electrodes;
• and
• an isolation region in or near a region of the III-N semiconductor material which has a high electric field or is at a low electric potential during device operation, the isolation region serving to improve the efficiency of hole collection from the III-N semiconductor material;
• wherein
• the isolation region is a p-type or nominally p-type region;
• and
• the gate is electrically isolated from the isolation region.