Shift register memory and driving method thereof
AssigneeKabushiki Kaisha Toshiba
InventorsYoshiaki FUKUZUMI, Hideaki AOCHI
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Abstract
A shift register memory according to the present embodiment includes a magnetic pillar including a plurality of magnetic layers and a plurality of nonmagnetic layers provided between the magnetic layers adjacent to each other. A stress application part applies a stress to the magnetic pillar. A magnetic-field application part applies a static magnetic field to the magnetic pillar. The stress application part applies the stress to the magnetic pillar in order to transfer magnetization states of the magnetic layers in a stacking direction of the magnetic layers.
Claims21
1-20. (canceled)
A semiconductor memory device, comprising:
- a plurality of first lines provided parallel with one another;
- a plurality of second lines intersecting the plurality of first lines;
- a plurality of magnetic tunnel junction (MTJ) elements being arranged to form triangle grids;
- and
- a plurality of transistors provided between one of the MTJ elements and one of the plurality of the first lines respectively, and gate electrodes of the plurality of transistors being connected to one of the second lines.
A semiconductor memory device, comprising:
- a first bit line and a second bit line provided adjacent to each other;
- a first, a second, a third and a fourth word line provided in order and intersecting the first and the second bit lines;
- a first transistor and a second transistor sharing one side with each other, the one side of the first and the second transistors connected to the first bit line, a gate electrode of the first transistor being connected to the first word line, and a gate electrode of the second transistor being connected to the second word line;
- first and second MTJ elements being connected to other sides of the first and second transistors, respectively;
- third and fourth transistors sharing one side with each other, the one side of the third and the fourth transistors connected to the second bit line, a gate electrode of the third transistor being connected to the third word line, and a gate electrode of the fourth transistor being connected to the fourth word line;
- and
- third and fourth MTJ elements being connected to other sides of the third and fourth transistors, respectively.
Dependencies are inferred from the claim text.