Bootstrap mos for high voltage applications

A device comprising:

• an n-type buried well region;
• a first P-type Buried Layer (PBL) over and contacting the n-type buried well region;
• a p-well region over and contacting the first PBL;
• a first n-well region and a second n-well region in a top portion of the p-well region, wherein the first n-well region and the second n-well region are separated from each other by the p-well region;
• a first n-type source region and a second n-type source region in the first n-well region and the second n-well region, respectively;
• a first HVNW region and a second HVNW region contacting opposite edges of the p-well region;
• a first gate stack overlapping a portion of the p-well region and a portion of the first HVNW region;
• and
• a second gate stack overlapping a portion of the p-well region and a portion of the second HVNW region.

A device comprising:

• a p-well region;
• a first High-Voltage N-type Well (HVNW) region and a second HVNW region contacting opposite edges of the p-well region;
• a P-type Buried Layer (PBL) having opposite edges in contact with the first HVNW region and the second HVNW region;
• a n-type buried well region underlying the PBL, wherein the p-well region and the n-type buried well region are in contact with a top surface and a bottom surface, respectively, of the PBL;
• a first n-well region in a top portion of the p-well region;
• a first n-type source region in the first n-well region;
• a first gate stack overlapping a portion of the p-well region and a portion of the second HVNW region;
• and
• a first channel region under the first gate stack, wherein the first channel region interconnects the first n-well region and the second HVNW region.