Insulated gate semiconductor device and method for manufacturing the same
AssigneeFuji Electric Co., Ltd.
InventorYuichi ONOZAWA
Life of this patent
Estimating the term…
Abstract
An insulated gate semiconductor device includes a region that is provided between trenches in which a gate electrode is filled through a gate insulating film in a surface layer of a substrate, includes a p base region and an n+ emitter region, and comes into conductive contact with an emitter electrode and a p-type floating region that is electrically insulated by an insulating film which is interposed between the p-type floating region and the emitter electrode. The p-type floating region is deeper than the trench and has a lower impurity concentration than the p base region.
Claims10
An insulated gate semiconductor device comprising:
- a first-conduction-type drift layer that is a semiconductor substrate;
- a second-conduction-type base region that is selectively formed on one main surface of the first-conduction-type drift layer;
- a first-conduction-type emitter region that is selectively formed in a surface of the second-conduction-type base region;
- a second-conduction-type semiconductor layer that is formed on the other main surface of the first-conduction-type drift layer;
- a plurality of trenches that have a depth greater than that of the second-conduction-type base region from the surface of the first-conduction-type emitter region and have a parallel-stripe-shaped planar pattern along a longitudinal direction of the first-conduction-type emitter region;
- and
- a gate electrode that is filled in each of the plurality of trenches with an insulating film interposed therebetween,
- wherein a plurality of surface regions interposed between the plurality of trenches include second-conduction-type floating regions that are electrically insulated and are alternately arranged, together with the second-conduction-type base region and the first-conduction-type emitter region which come into conductive contact with an emitter electrode, and
- the second-conduction-type floating region is deeper than the trench and has a lower impurity concentration than the second-conduction-type base region.
A method for manufacturing an insulated gate semiconductor device which includes a first-conduction-type drift layer that is a semiconductor substrate, a second-conduction-type base region that is selectively formed on one main surface of the first-conduction-type drift layer, a first-conduction-type emitter region that is selectively formed in a surface of the second-conduction-type base region, a second-conduction-type semiconductor layer that is formed on the other main surface of the first-conduction-type drift layer, a plurality of trenches that have a depth greater than that of the second-conduction-type base region from the surface of the first-conduction-type emitter region and have a parallel-stripe-shaped planar pattern along a longitudinal direction of the first-conduction-type emitter region, and a gate electrode that is filled in each of the plurality of trenches with an insulating film interposed therebetween and in which a plurality of surface regions interposed between the plurality of trenches include second-conduction-type floating regions that are electrically insulated and are alternately arranged, together with the second-conduction-type base region and the first-conduction-type emitter region which come into conductive contact with an emitter electrode, and the second-conduction-type floating region is deeper than the trench and has a lower impurity concentration than the second-conduction-type base region, the method comprising:
- forming the second-conduction-type floating region at the same time as a guard ring which is provided in a breakdown voltage structure region surrounding the outermost circumference of the second-conduction-type floating region in order to relax an electric field is formed.
A method for manufacturing an insulated gate semiconductor device which includes a first-conduction-type drift layer that is a semiconductor substrate, a second-conduction-type base region that is selectively formed on one main surface of the first-conduction-type drift layer, a first-conduction-type emitter region that is selectively formed in a surface of the second-conduction-type base region, a second-conduction-type semiconductor layer that is formed on the other main surface of the first-conduction-type drift layer, a plurality of trenches that have a depth greater than that of the second-conduction-type base region from the surface of the first-conduction-type emitter region and have a parallel-stripe-shaped planar pattern along a longitudinal direction of the first-conduction-type emitter region, and a gate electrode that is filled in each of the plurality of trenches with an insulating film interposed therebetween and in which a plurality of surface regions interposed between the plurality of trenches include second-conduction-type floating regions that are electrically insulated and are alternately arranged, together with the second-conduction-type base region and the first-conduction-type emitter region which come into conductive contact with an emitter electrode, and the second-conduction-type floating region is deeper than the trench and has a lower impurity concentration than the second-conduction-type base region, the method comprising:
- forming the second-conduction-type floating region at the same time as a second-conduction-type RESURF region which is provided in a breakdown voltage structure region surrounding the outermost circumference of the second-conduction-type floating region in order to relax an electric field is formed.
Dependencies are inferred from the claim text.