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US 2014/0231741 A1Published application
Planar resistive memory integration
AssigneeUnity Semiconductor Corporation
InventorsLidia Vereen, Bruce Lynn Bateman, Louis Parillo, Elizabeth Friend, David Eggleston
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Abstract
In an example, a single damascene structure is formed by, for example, providing a dielectric layer, forming a void in the dielectric layer, and forming a portion of a first two-terminal resistive memory cell and a portion of a second two-terminal resistive memory cell within the void. The portions of the two-terminal resistive memory cells may be vertically stacked within the void.
Claims24
1-23. (canceled)
A method, comprising:
- providing a dielectric layer;
- forming a void in the dielectric layer;
- and
- forming a structure in the void, the structure comprising:
- a first layer of memory material;
- an interconnect above the first layer of memory material;
- and
- a second layer of memory material above the interconnect.
5 more elements
An apparatus, comprising:
- a dielectric layer;
- a void formed in the dielectric layer;
- a portion of a first two-terminal resistive memory cell located within the void;
- a portion of a second two-terminal resistive memory cell located above the first two- terminal resistive memory cell and within the void,
- wherein the portion of the second two-terminal resistive memory cell that is located within the void is electrically connected to the portion of the first two-terminal memory cell that is located within the void by a conductive material formed in the void.
2 more elements
Dependencies are inferred from the claim text.