# US 2014/0229957 A1 · Multi-Core Processor System > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0229957 A1 - Document ID: US20140229957A1 - Status: Published application - Kind: A1 - Application number: 14/263,338 - Filed: 2014-04-28 - Published: 2014-08-14 - Earliest claimed: 2012-02-01 - Assignees: Huawei Technologies Co., Ltd. - Applicants: Huawei Technologies Co., Ltd. - Inventors: Weiguo Zhang; Libo Wu - Web page: https://patentgrep.com/patent/US20140229957A1 ## CPC - G06F 9/546: {Message passing systems or structures, e.g. queues} - G06F 2209/548: Queue - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract The present invention provides a multi-core processor system, including: multiple central processor units and multiple groups of level-one hardware message queues. Each central processor unit is separately connected to a group of level-one hardware message queues and is configured to process messages in the level-one hardware message queues. Each group of level-one hardware message queues includes multiple level-one hardware message queues. Moreover, in each group of level-one hardware message queues, a level-one hardware message queue having a higher priority is scheduled preferentially, and level-one hardware message queues having the same priority are scheduled in a round-robin manner according to round robin scheduling weights. Through the multi-core processor system provided in the present invention, the efficiency and performance of the multi-core processor system are improved. ## Claims ### Claim 1 A multi-core processor system comprising: multiple central processor units each of which is separately connected to a group of level-one hardware message queues configured to process messages in the level-one hardware message queues, wherein the group of level-one hardware message queues is further connected to a group of level-two hardware message queues configured to push messages to the level-one hardware message queues. ### Claim 2 (depends on 1) The multi-core processor system according to claim 1, wherein a read speed of the level-one hardware message queues is higher than that of the level-two hardware message queues, and the number of messages supported by the level-one hardware message queues is smaller than the number of messages supported by the level-two hardware message queues. ### Claim 3 (depends on 1) The multi-core processor system according to claim 1, wherein in the level-one hardware message queues, a level-one hardware message queue having a higher priority is scheduled preferentially, and level-one hardware message queues having the same priority are scheduled in a round-robin manner according to round robin scheduling weights. ### Claim 4 (depends on 1) The multi-core processor system according to claim 1, wherein the group of level-two hardware message queues is further connected to a group of other level-one hardware message queues. ### Claim 5 (depends on 4) The multi-core processor system according to claim 4, wherein messages in the level-two hardware message queues are preferentially pushed to a level-one hardware message queue having a minimum number of cached messages between the level-one hardware message queues and the other level-one hardware message queues. ### Claim 6 (depends on 4) The multi-core processor system according to claim 4, wherein the level-one hardware message queues has a different priority as the other level-one hardware message queues, messages in the level-two hardware message queues are preferentially pushed to a group of level-one hardware message queues having a higher priority between the level-one hardware message queues and the other level-one hardware message queues. ### Claim 7 (depends on 4) The multi-core processor system according to claim 4, wherein messages in the level-two hardware message queues are pushed to the level-one hardware message queues and the other level-one hardware message queues, according to message flow ordering based on tag value. ### Claim 8 (depends on 1) The multi-core processor system according to claim 1, wherein in the level-two hardware message queues, a level-two hardware message queue having a higher priority is scheduled preferentially, and level-two hardware message queues having the same priority are scheduled in a round-robin manner according to round robin scheduling weights. ### Claim 9 (depends on 1) The multi-core processor system according to claim 1, wherein messages in the level-two hardware message queues are pushed to the level-one hardware message queues when messages in the level-one hardware message queues are empty or lower than a preset waterline value. ### Claim 10 A multi-core processor system comprising: multiple central processor units each of which is separately connected to a group of level-one hardware message queues configured to process messages in the level-one hardware message queues, wherein the group of level-one hardware message queues is further connected to a group of level-two hardware message queues configured to push messages to the level-one hardware message queues, and wherein the level-two hardware message queues is further connected to a group of other level-one hardware message queues. ### Claim 11 (depends on 10) The multi-core processor system according to claim 10, wherein a read speed of the level-one hardware message queues is higher than that of the level-two hardware message queues, and the number of messages supported by the level-one hardware message queues is smaller than the number of messages supported by the level-two hardware message queues. ### Claim 12 (depends on 10) The multi-core processor system according to claim 10, wherein in the group of level-one hardware message queues, a level-one hardware message queue having a higher priority is scheduled preferentially, and level-one hardware message queues having the same priority are scheduled in a round-robin manner according to round robin scheduling weights. ### Claim 13 (depends on 10) The multi-core processor system according to claim 10, wherein messages in the level-two hardware message queues are preferentially pushed to a level-one hardware message queue having a minimum number of cached messages between the level-one hardware message queues and the other level-one hardware message queues. ### Claim 14 (depends on 10) The multi-core processor system according to claim 10, wherein the level-one hardware message queues has a different priority as the other level-one hardware message queues, messages in the level-two hardware message queues are preferentially pushed to a group of level-one hardware message queues having a higher priority between the level-one hardware message queues and the other level-one hardware message queues. ### Claim 15 (depends on 10) The multi-core processor system according to claim 10, wherein messages in the level-two hardware message queues are pushed to the level-one hardware message queues and the other level-one hardware message queues, according to message flow ordering based on tag value. ### Claim 16 (depends on 10) The multi-core processor system according to claim 10, wherein in the level-two hardware message queues, a level-two hardware message queue having a higher priority is scheduled preferentially, and level-two hardware message queues having the same priority are scheduled in a round-robin manner according to round robin scheduling weights. ### Claim 17 (depends on 10) The multi-core processor system according to claim 10, wherein messages in the group of level-two hardware message queues are pushed to the level-one hardware message queues when messages in the level-one hardware message queues are empty or lower than a preset waterline value.