System and method of circuit layout for multiple cells
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChia-Chu LIU, Kuei Shun CHEN
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Abstract
A circuit layout method comprises inputting layout data into a circuit layout system. The layout data represents a plurality of patterns in a plurality of cells. Each pattern of the plurality of patterns has a plurality of runs, ends, and corners. The method also comprises specifying a plurality of G1-rule criteria. The method further comprises reviewing a representation of G0-space and G0 rule violations for each cell of the plurality of cells. The method additionally comprises inputting an adjustment to the layout data. The method also comprises reviewing a representation of adjusted cell edge spacings, and selecting to output a final layout.
Claims20
A circuit layout method comprising:
- inputting layout data into a circuit layout system, said layout data representing a plurality of patterns in a plurality of cells, each pattern of the plurality of patterns having a plurality of runs, ends, and corners;
- specifying a plurality of G1-rule criteria;
- inputting an adjustment to the layout data based on a representation of G0-space and G0 rule violations for each cell of the plurality of cells to output a representation of adjusted cell edge spacings;
- and
- selecting to output a final layout.
A circuit layout method comprising:
- re-assigning a first set of mask patterns to a second mask and a second set of mask patterns to a first mask based on a determination that a near edge pattern of a first cell and a near edge pattern of a second cell are both assigned to the first mask or the second mask;
- adjusting cell edge spacings, using a computer, at the shared edge in the first and second cell according to a minimum spacing rule and a G1-rule, wherein the G1-rule is a distance between a next edge pattern of the first cell and the shared edge or between the next edge pattern of the first cell and the near edge pattern of the second cell, and the next edge pattern of the first cell is different from the near edge pattern of the first cell;
- and
- outputting a representation of layout data representing the first cell and the second cell having adjusted cell edge spacings.
A system comprising:
- a computer readable storage medium containing data representing an integrated circuit (IC) layout, said layout comprising, in one layer, a plurality of cells having patterns having a plurality of runs, ends, and corners;
- and
- a processor coupled to read the storage medium, the processor configured to:
- process received input layout data related to the IC layout having one or more cells to determine if any G0-space and G0 rule violations exist for each cell of the plurality of cells;
- generate a representation of determined G0-space and G0 rule violations for each cell;
- process received adjustment data to adjust cell edge spacing in the layout data to correct determined G0-space and G0 rule violations for each cell, the adjustment data being in compliance with at least one G1-rule;
- generate a representation of adjusted cell edge spacings;
- and
- output a final layout.
Dependencies are inferred from the claim text.