Instruction-set architecture for programmable cyclic redundancy check (crc) computations

A method comprising:

• performing a sequence of operations for a Cyclic Redundancy Check (CRC) instruction, the CRC instruction specifying a first operand and a second operand, the sequence of operations to perform a Cyclic Redundancy Check (CRC) operation on a 2n-bit data block stored in the second operand using a programmable n-bit polynomial stored in the first operand, comprising:
• expanding the programmable polynomial to provide a pre-computed polynomial K;
• and
• performing a sequence of micro-operations on the 2n-bit data block using the programmable n-bit polynomial and a current n-bit residue stored in the first operand and the pre-computed polynomial K to provide an n-bit residue for the 2n-bit data block, wherein performing the sequence of micro-operations comprises reducing an n+8-bit data using the pre-computed polynomial K to provide an n+4-bit intermediate residue and reducing the n+4 intermediate residue to the n-bit residue using the programmable n-bit polynomial.

A system comprising:

• a processor including:
• an execution unit to execute a Cyclic Redundancy Check (CRC) instruction that identifies a first operand that stores a current n-bit residue and a programmable n-bit polynomial and a second operand that stores a 2n-bit data block, the CRC instruction to cause the execution unit to:
• perform a sequence of micro-operations to expand the programmable n-bit polynomial to provide a pre-computed polynomial K, shuffle an n-bit portion from the first operand and an n-bit portion from the second operand based on an immediate data, and reduce an n-bit portion of the 2n-bit data block using the programmable n-bit polynomial, the current n-bit residue of the first operand and the pre-computed polynomial K, to provide an n-bit residue;
• and
• a dynamic random access memory coupled to the processor.