Systems and Methods for Distributed Low Density Parity Check Decoding

A method for data processing, the method comprising:

• providing a distributed architecture data decoder circuit, the distributed architecture data decoder circuit comprising:
• a low density parity check data decoder circuit including at least a first data decoder engine and a second data decoder engine each electrically coupled to a common circuit, wherein the first data decoder engine is operable to perform variable node updating for a first portion of a codeword and the second data decoder engine is operable to perform variable node updating for a second portion of the codeword, and wherein the common circuit is operable to perform a syndrome calculation on a combination of at least the first portion and the second portion of the codeword;
• generating a first new check node to variable node message in the first data decoder engine;
• adding a first portion of a codeword to the first new check node to variable node message to yield a first interim output in the first data decoder engine;
• rearranging the first interim output to yield a first sub-message in the first data decoder engine;
• generating a second new check node to variable node message in the second data decoder engine;
• adding a second portion of the codeword to the second new check node to variable node message to yield a second interim output in the second data decoder engine;
• rearranging the second interim output to yield a second sub-message in the second data decoder engine;
• and
• providing the second sub-message to the common circuit.

A data storage device, the device comprising:

• a storage medium operable to store information corresponding to a codeword;
• a head assembly disposed in relation to the storage medium and operable to provide a sensed signal corresponding to the information;
• a read channel circuit including:
• an analog front end circuit operable to provide an analog signal corresponding to the sensed signal;
• an analog to digital converter circuit operable to sample the analog signal to yield a series of digital samples;
• an equalizer circuit operable to equalize the digital samples corresponding to the data set to yield the codeword;
• a data decoder circuit operable to apply a low density parity check decode algorithm to a decoder input derived from the codeword, wherein the data decoder circuit includes at least a first data decoder engine and a second data decoder engine each electrically coupled to a common circuit, wherein the first data decoder engine is operable to perform variable node updating for a first portion of a codeword and the second data decoder engine is operable to perform variable node updating for a second portion of the codeword, and wherein the common circuit is operable to perform a syndrome calculation on a combination of at least the first portion and the second portion of the codeword.