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US 2014/0229797 A1Published application
Error correcting code scheme utilizing reserved space
AssigneeIntel Corporation
InventorsRajat Agrawal, Debaleena Das, Kai Cheng
Life of this patent
Estimating the term…
Abstract
Methods, techniques, systems and apparatuses for utilizing reserved space for error correcting functionality. A cache line (“reserved line”) in a plurality of cache lines to store error correcting code (ECC) data is utilized for storing ECC data corresponding to other cache lines within the plurality of cache lines when a memory device has failed.
Claims21
A method comprising:
- utilizing a cache line (“reserved line”) in a plurality of cache lines to store error correcting code (ECC) data;
- storing within the reserved line ECC data corresponding to other cache lines within the plurality of cache lines.
A memory controller comprising:
- an interface to send data to and receive data from one or more memory devices;
- and
- control logic coupled with the interface, the control logic to cause a selected cache line (“reserved line”) in a plurality of cache lines to store error correcting code (ECC) data, and to cause to be stored within the reserved line ECC data corresponding to other cache lines within the plurality of cache lines.
A system comprising:
- one or more memory devices;
- and
- control logic coupled with the one or more memory devices, the control logic to cause a selected cache line (“reserved line”) in a plurality of cache lines to store error correcting code (ECC) data, and to cause to be stored within the reserved line ECC data corresponding to other cache lines within the plurality of cache lines.
Dependencies are inferred from the claim text.