Using ECC Data for Write Deduplication Processing

An apparatus comprising:

• a non-volatile (NV) write buffer adapted to store first write data having a selected logical address;
• an NV main memory coupled to the write buffer;
• and
• a storage manager adapted to transfer a copy of the first write data and a corresponding first ECC data from the write buffer to the main memory, the first ECC data adapted to detect up to a selected number of bit errors in the transferred copy of the first write data during a subsequent readback operation, wherein the storage manager is further adapted to, responsive to receipt of second write data having the selected logical address in the write buffer, generate second ECC data associated with the second write data and store the second write data to the main memory responsive to a mismatch between the first ECC data and the second ECC data.

An apparatus comprising:

• a non-volatile (NV) write buffer;
• a multi-tier main memory structure comprising a plurality of NV memory tiers arranged in a priority order and each having different storage attributes;
• and
• a controller adapted to temporarily cache input write data in the write buffer pending transfer to the main memory structure, the controller comprising a programmable processor having associated programming to:
• generate and store a first data object and an associated first ECC data set in the main memory structure responsive to a first set of data blocks in the write buffer having a selected logical address;
• generate a second data object and an associated second ECC data set responsive to receipt of a second set of data blocks in the write buffer having the selected logical address;
• and
• store the second data object and the second ECC data set in the main memory structure responsive to a mismatch between the first ECC data set and the second ECC data set.