At-speed scan testing of interface functional logic of an embedded memory or other circuit core

Abstract

An integrated circuit comprises scan test circuitry and at least one circuit core coupled to the scan test circuitry. The scan test circuitry comprises input and output scan chains coupled to respective input and output interfaces of the circuit core via respective functional logic blocks, and interface signal selection circuitry. The interface signal selection circuitry is configured to select a particular one of a functional input signal and a plurality of scan test input signals for application to one or more designated input signal lines of the input interface of the circuit core responsive to one or more control signals. By way of example only, the first and second scan test input signals may comprise respective first and second distinct address values and the designated input signal lines of the input interface of the circuit core may comprise address input signal lines of an embedded memory.

Dependencies are inferred from the claim text.