Dynamic hard error detection
AssigneeInternational Business Machines Corporation
InventorsPradip Bose, Alan Gara, Hans M. Jacobson
Life of this patent
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Abstract
An apparatus for detecting hard errors in a circuit includes a storage device and a processing circuit. The storage has stored therein test data and normal data. The processing circuit includes combinational logic in series with at least one set of input latches and at least one set of output latches. The apparatus includes a test control module configured to control the processing circuit to halt a flow of normal data through the processing circuit and run the test data through the processing circuit while subjecting the processing circuit to a stress condition.
Claims17
An apparatus for detecting hard errors, comprising:
- a storage device having stored therein test data and normal data;
- and
- a processing circuit comprising combinational logic in series with at least one set of input latches and at least one set of output latches;
- and
- a test control module configured to control the processing circuit to halt a flow of normal data through the processing circuit and run the test data through the processing circuit while subjecting the processing circuit to a stress condition.
A computer program product for testing a circuit, comprising:
- a tangible computer-readable storage medium having stored thereon a computer program for performing a method, the method comprising:
- halting a flow of normal data through the circuit;
- running test data through the circuit while subjecting the circuit to a stress condition;
- and
- determining whether a hard error exists in the circuit based on the running of the test data.
-25. (canceled)
Dependencies are inferred from the claim text.